Fan-out semiconductor package

1. A semiconductor package comprising:

a semiconductor chip having an active surface, having connection pads disposed thereon, and an inactive surface, opposing the active surface;

an encapsulant covering the inactive surface of the semiconductor chip;

a thermally conductive via penetrating through at least a portion of the encapsulant on the inactive surface of the semiconductor chip and physically spaced apart from the inactive surface of the semiconductor chip;

a thermally conductive pattern layer disposed on the encapsulant and connected to the thermally conductive via;

a cover layer disposed on the encapsulant and having openings opening at least portions of the thermally conductive pattern layer disposed facing the inactive surface, the openings exposing a portion of side surfaces of the cover layer; and

a connection structure disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads,

wherein the openings are not filled.

2. The semiconductor package of claim 1 , wherein the encapsulant fills at least portions of a region in which the inactive surface of the semiconductor chip and the thermally conductive via are physically spaced apart from each other.

3. The semiconductor package of claim 1 , wherein the inactive surface of the semiconductor chip and the thermally conductive via are physically spaced apart from each other only by a portion of the encapsulant filling between the inactive surface of the semiconductor chip and the thermally conductive via.

4. The semiconductor package of claim 1 , wherein a distance by which the inactive surface of the semiconductor chip and the thermally conductive via are physically spaced apart from each other is 1 μm to 5 μm.

5. The semiconductor package of claim 1 , wherein the thermally conductive via has a tapered shape of which a width of a cross section becomes narrow toward the inactive surface of the semiconductor chip.

6. The semiconductor package of claim 1 , wherein the thermally conductive via includes a layer formed of only a metal.

7. The semiconductor package of claim 1 , wherein the thermally conductive pattern layer protrudes from the encapsulant.

8. The semiconductor package of claim 1 , wherein the thermally conductive pattern layer is disposed to directly face the inactive surface.

9. The semiconductor package of claim 1 , wherein the thermally conductive via and the thermally conductive pattern layer are integrated with each other without having a boundary therebetween.

10. The semiconductor package of claim 1 , wherein the thermally conductive pattern layer is embedded in the encapsulant, and has one surface exposed from the encapsulant.

11. The semiconductor package of claim 10 , wherein an upper surface of the thermally conductive pattern layer and an upper surface of the encapsulant are substantially coplanar with each other.

12. The semiconductor package of claim 10 , wherein the thermally conductive pattern layer is disposed to directly face the inactive surface.

13. The semiconductor package of claim 10 , wherein the thermally conductive via penetrates through the thermally conductive pattern layer.

14. The semiconductor package of claim 1 , further comprising a frame having a through-hole,

wherein the semiconductor chip is disposed in the through-hole,

the encapsulant covers at least portions of the frame, and

the encapsulant fills at least portions of the through-hole.

15. The semiconductor package of claim 14 , wherein the frame includes a plurality of wiring layers,

the plurality of wiring layers are electrically connected to the connection pads,

a wiring pattern layer is disposed on or in the encapsulant, and

the wiring pattern layer is electrically connected to an uppermost wiring layer of the plurality of wiring layers through a wiring via penetrating through at least a portion of the encapsulant.

16. The semiconductor package of claim 14 , wherein the frame includes a first insulating layer in contact with the connection structure, a first wiring layer embedded in the first insulating layer and in contact with the connection structure, a second wiring layer disposed on the other surface of the first insulating layer opposing one surface of the first insulating layer in which the first wiring layer is embedded, a second insulating layer disposed on the first insulating layer and covering the second wiring layer, and a third wiring layer disposed on the second insulating layer, and

the first to third wiring layers are electrically connected to the connection pads.

17. The semiconductor package of claim 16 , wherein the frame further includes a third insulating layer disposed on the second insulating layer and covering the third wiring layer and a fourth wiring layer disposed on the third insulating layer, and

the fourth wiring layer is electrically connected to the connection pads.

18. The semiconductor package of claim 14 , wherein the frame includes a first insulating layer, a first wiring layer disposed on one surface of the first insulating layer, a second wiring layer disposed on the other surface of the first insulating layer, a second insulating layer disposed on one surface of the first insulating layer and covering the first wiring layer, a third wiring layer disposed on the second insulating layer, a third insulating layer disposed on the other surface of the first insulating layer and covering the second wiring layer, and a fourth wiring layer disposed on the third insulating layer, and

the first to fourth wiring layers are electrically connected to the connection pads.

19. The semiconductor package of claim 1 , wherein a thermal conductivity of the encapsulant is about 0.6 W/m° C. to 0.8 W/m° C.

20. The semiconductor package of claim 1 , wherein a thermal conductivity of the encapsulant is greater than that of an insulating layer of the connection structure.

21. A semiconductor package comprising:

a semiconductor chip having an active surface, having connection pads disposed thereon, and an inactive surface, opposing the active surface;

an encapsulant layer covering the semiconductor chip;

a thermally conductive via penetrating into the encapsulant layer and spaced apart from the semiconductor chip only by a portion of the encapsulant layer disposed between the thermally conductive via and the semiconductor chip;

a thermally conductive pattern layer connected to the thermally conductive via;

a cover layer disposed on the encapsulant layer and having openings opening at least portions of the thermally conductive pattern layer;

a surface treatment layer disposed on opened surfaces of the thermally conductive pattern layer, a thickest portion of the surface treatment layer being less than a thickest portion of the cover layer; and

a connection structure disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads.

22. The semiconductor package of claim 21 , wherein a distance by which the semiconductor chip and the thermally conductive via are spaced apart from each other is 5 μm or less.

23. The semiconductor package of claim 21 , wherein the thermally conductive via has a tapered shape of which a width of a cross section becomes narrow toward the semiconductor chip.

24. The semiconductor package of claim 21 ,

wherein the thermally conductive via extends from the thermally conductive pattern layer towards the semiconductor chip.

25. The semiconductor package of claim 24 , wherein the thermally conductive pattern layer protrudes on the encapsulant layer.

26. The semiconductor package of claim 21 , wherein

the thermally conductive pattern layer is embedded in the encapsulant layer and has one surface exposed from the encapsulant layer.

27. The semiconductor package of claim 21 , further comprising a frame having a through-hole,

wherein the semiconductor chip is disposed in the through-hole, and

the encapsulant layer extends from the inactive surface of the semiconductor chip to fill at least portions of the through-hole.

28. The semiconductor package of claim 21 , wherein a thermal conductivity of the encapsulant layer is about 0.6 W/m° C. to 0.8 W/m° C.