Semiconductor copper metallization structure and related methods
View Patent ↗Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip.
1. A semiconductor package comprising:
a die comprising a pad on a first side of the die, the pad comprising one of aluminum and copper (AlCu); aluminum, copper and silicon (AlCuSi); aluminum, copper, and tungsten (AlCuW); aluminum silicon (AlSi); or any combination thereof;
a first copper layer coupled directly over and to the pad;
a second copper layer coupled over the first copper layer; and
a metal layer comprised on a second side of the die opposite the first side of the die, wherein an implanted doped layer is formed in the second side of the die.
2. A semiconductor package of claim 1 , wherein a width of the first copper layer above the pad is wider than a width of the second copper layer above the pad.
3. The semiconductor package of claim 1 , further comprising a metal coating forming one of a metal cap on a top of the second copper layer or a full metal coverage of the first and the second copper layers, the metal coating applied through one of electroless plating or electrolytic plating.
4. The semiconductor package of claim 3 , wherein the metal coating comprises one of nickel and gold (Ni/Au); nickel, palladium, and gold (Ni/Pd/Au); nickel and silver (Ni/Ag); or any combination thereof.
5. A semiconductor package comprising:
a die comprising a pad on a first side of the die, the pad comprising one of aluminum and copper (AlCu); aluminum, copper and silicon (AlCuSi); aluminum, copper, and tungsten (AlCuW); aluminum silicon (AlSi); or any combination thereof;
a first copper layer coupled directly over and to the pad;
a second copper layer coupled over the first copper layer; and
a metal layer comprised on a second side of the die opposite the first side of the die, wherein an implanted doped layer is formed in the second side of the die;
wherein a width of the first copper layer above the pad is wider than a width of the second copper layer above the pad; and
wherein the first and second copper layers are configured to one of bond with a heavy copper wire or solder with a copper clip.
6. A semiconductor package of claim 5 , wherein a width of the first copper layer above the pad is wider than a width of the second copper layer above the pad.
7. The semiconductor package of claim 5 , further comprising a metal coating forming one of a metal cap on a top of the second copper layer or a full metal coverage of the first and the second copper layers, the metal coating applied through one of electroless plating or electrolytic plating.
8. The semiconductor package of claim 7 , wherein the metal coating comprises one of nickel and gold (Ni/Au); nickel, palladium, and gold (Ni/Pd/Au); nickel and silver (Ni/Ag); or any combination thereof.
9. A semiconductor package comprising:
a die comprising a first side and a second side, wherein the second side comprises an implanted doped layer;
a pad comprised on the first side of the die, the pad comprising one of aluminum copper (AlCu); aluminum copper silicon (AlCuSi); aluminum copper tungsten (AlCuW); aluminum silicon (AlSi); and any combination thereof;
a first copper layer coupled over the pad;
a second copper layer coupled over the first copper layer;
a first metal layer comprised on a second side of the die; and
a second metal layer directly coupled to the first metal layer;
wherein a width of the first copper layer above the pad is wider than a width of the second copper layer above the pad.
10. A semiconductor package of claim 9 , wherein the first and second copper layers are configured to one of bond with a heavy copper wire and solder with a copper clip.
11. The semiconductor package of claim 9 , further comprising a metal coating forming one of a metal cap on a top of the second copper layer or a full metal coverage of the first and the second copper layers, the metal coating applied through one of electroless plating and electrolytic plating.
12. The semiconductor package of claim 11 , wherein the metal coating comprises one of nickel and gold (Ni/Au); nickel, palladium, and gold (Ni/Pd/Au); nickel and silver (Ni/Ag); or any combination thereof.
13. The semiconductor package of claim 9 , wherein the first metal layer comprises aluminum.
14. The semiconductor package of claim 13 , wherein the second metal layer comprises one of titanium, nickel, or silver.
15. The semiconductor package of claim 9 , wherein the implanted doped layer comprises one of boron, phosphorus, or any combination thereof.
16. The semiconductor package of claim 9 , further comprising a device comprised in the second side of the die.
17. The semiconductor package of claim 16 , wherein the device comprises one of an insulated gate bipolar transistor (IGBT) and a diode.
18. The semiconductor package of claim 10 , wherein the heavy copper wire is more than 5 mil in diameter.