Trusted booting by hardware root of trust (HRoT) device

1. A method running on a security device, the method comprising:

executing a first secure boot code from a first memory by one of a plurality of cores of a processor, wherein the plurality of cores runs in a secure world;

executing a first-stage boot loader (FSBL) from a second memory;

executing a security monitoring application to validate the security device;

in response to the security device being validated, switching some of the plurality of cores from the secure world to a normal world, wherein at least one of the plurality of cores remains in the secure world to communicate with the security monitoring application;

executing a second-stage boot loader (SSBL); and

monitoring, via the security monitoring application, status of the security device and communications between the security device and at least one external system,

wherein a software portion of the security monitoring application runs on the second memory and a hardware portion of the security monitoring application runs on a programmable logic (PL) area.

2. The method of claim 1 , wherein the FSBL is authenticated, decrypted, and loaded onto the second memory before the FSBL is executed.

3. The method of claim 1 , further comprising:

loading at least one secure application that is executed by at least one of the plurality of cores that runs in the secure world, wherein the at least one secure application is configured to communicate with the security monitoring application.

4. The method of claim 3 , wherein the at least one secure application is configured to communicate with a trusted platform module (TPM) device.

5. The method of claim 4 , further comprising:

loading at least one regular application that is executed by one of the plurality of cores that runs in the normal world,

wherein the at least one regular application communicates with the at least one secure application to perform any transactions.

6. The method of claim 1 , wherein only one of the plurality of cores operates to execute the first secure boot code.

7. The method of claim 1 , wherein the SSBL is authenticated, decrypted, and stored into the second memory before the SSBL is executed.

8. A system for secure booting, the system comprising:

a security device comprising a processor, wherein the processor comprises a plurality of cores, a first memory, and a second memory,

wherein the plurality of cores is configured to:

execute a first secure boot code from the first memory by one of the plurality of cores, wherein the plurality of cores runs in a secure world;

execute a first-stage boot loader (FSBL) from the second memory;

execute a security monitoring application to validate the security device;

in response to the security device being validated, switch some of the plurality of cores from the secure world to a normal world, wherein at least one of the plurality of cores remains in the secure world to communicate with the security monitoring application;

execute a second-stage boot loader (SSBL); and

monitor, via the security monitoring application, status of the security device and communications between the security device and at least one external system,

further comprising a programmable logic (PL) area, wherein a software portion of the security monitoring application runs on the second memory and a hardware portion of the security monitoring application runs on the PL area.

9. The system of claim 8 , wherein the security device comprises a Hardware Root of Trust (HRoT) device.

10. The system of claim 8 , wherein the first memory comprises an internal boot read-only memory (ROM).

11. The system of claim 8 , wherein the second memory comprises an on-chip memory (OCM).

12. The system of claim 8 , wherein the FSBL is authenticated, decrypted, and loaded onto the second memory before the FSBL is executed.

13. The system of claim 8 , wherein the plurality of processors is further configured to:

load at least one secure application that is executed by at least one of the plurality of cores that runs in the secure world, wherein the at least one secure application is configured to communicate with the security monitoring application.

14. A Hardware Root of Trust (HRoT) device, the device comprising:

a processor having a plurality of cores, a first memory and a second memory,

wherein the plurality of cores is configured to:

execute a first secure boot code from the first memory, wherein the plurality of cores runs in a secure world;

execute a first-stage boot loader (FSBL) from the second memory;

execute a security monitoring application to validate the HRoT device;

in response to the computer being validated, switch some of the plurality of cores from the secure world to a normal world, wherein at least one of the plurality of cores remains in the secure world to communicate with the security monitoring application;

execute a second-stage boot loader (SSBL); and

monitor, via the security monitoring application, status of the HRoT device and communications between the HRoT device and at least one external system,

the HRoT device further comprising a programmable logic (PL) area, wherein a software portion of the security monitoring application runs on the plurality of cores and a hardware portion of the security monitoring application runs on the PL area.

15. The HRoT device of claim 14 , wherein the first memory comprises an internal boot read-only memory (ROM).

16. The HRoT device of claim 14 , wherein the second memory comprises an on-chip memory (OCM).