Multiple-pipeline architecture with special number detection

1. A method for computation, with special number detection, in a computational device having a core with a multiple-pipeline architecture, the method comprising:

running, in parallel, a first and second pipeline of data from a memory, wherein the first pipeline is configured to receive a first operand from the memory and the second pipeline is configured to receive a second operand from the memory, and wherein the first operand and the second operand are input operands for performing a computational operation and the first pipeline operates at least one cycle ahead of the second pipeline;

generating a memory address in the memory for the first operand;

reading, on the first pipeline, the first operand from the generated memory address; and

detecting if the first operand is a special number, wherein a special number is a numerical value that yields a predictable operation result of the computational operation; and

storing a result of the computational operation in the memory based on the detection of whether the first operand is the special number.

2. The method of claim 1 , wherein upon determining the first operand is a special number, the method further comprises:

retrieving the result corresponding to the predictable operation result of the computational operation that is yielded by the detected special number; and

storing the retrieved result in the memory for the first and second pipeline.

3. The method of claim 2 , wherein the computational operation is a multiplication operation and wherein the first operand is detected as being a special number comprising a numerical value of zero, the method further comprising:

preventing a generation of a memory address for the second operand.

4. The method of claim 2 , wherein the computational operation is a multiplication operation and wherein the first operand is detected as being a special number comprising a numerical value of one, the method further comprising:

generating a memory address for the second operand;

reading, on the second pipeline, the second operand from the generated memory address; and

assigning a value of the result as being equal to a value of the second operand.

5. The method of claim 1 , wherein upon determining the first operand is not a special number, the method further comprises:

generating a memory address in the memory for the second operand;

reading, on the second pipeline, the second operand from the generated memory address;

performing the computational operation on the first and second operand; and

storing the result of the performed computational operation in the memory for the first and second pipeline.

6. A computational device for performing a computational operation with special number detection, the computational device comprising:

a core having a plurality of processing units configured to perform operations, the core comprising:

a memory configured to store operands;

a first pipeline configured to read a first operand from the memory based on a memory address being generated for the first operand;

a second pipeline configured to receive a second operand from the memory, wherein the first operand and the second operand are input operands for performing the computational operation and the first pipeline operates at least one cycle ahead of the second pipeline;

a detector configured to detect if the first operand is a special number, wherein the special number is a numerical value that yields a predictable operation result of the computational operation, and

wherein the core is further configured to store a result in the memory based on the detection whether the first operand is a special number.

7. The computation device of claim 6 , wherein if the first operand is a special number:

the core is further configured to retrieve the predictable operation result of the computational operation that is yielded by the detected special number; and

the core is also configured to store the retrieved result in the memory for the first and second pipeline.

8. The computational device of claim 7 , wherein the computational operation is a multiplication operation and wherein the first operand is detected as being a special number comprising a numerical value of zero:

the core is further configured to stop a generation of a memory address for the second operand.

9. The computational device of claim 7 , wherein the computational operation is a multiplication operation and wherein the first operand is detected as being a special number comprising a numerical value of one:

the core is further configured to generate a memory address for the second operand;

the second pipeline is configured to read the second operand from the generated memory address; and

the core is configured to assign a value of the result as being equal to a value of the second operand.

10. The computation device of claim 6 , wherein if the first operand is not a special number:

the core is further configured to generate a memory address in the memory for the second operand;

the second pipeline is configured to read the second operand from the generated memory address;

a processing unit of the core is further configured to perform the computational operation on the first and second operand; and

the core is configured to store the result of the performed computational operation in the memory for the first and second pipeline.

11. The computational device of claim 6 , wherein the memory comprises a plurality of storage cells, the plurality of storage cells further comprising at least one shared memory storage cell comprising data to be broadcasted to the first pipeline and at least one private memory storage cell comprising data to be read to the second pipeline.

12. The computational device of claim 6 , wherein the core comprises at least one processing unit array.

13. The computational device of claim 6 , wherein the core includes a Single Instruction Multiple Data (SIMD) architecture.

14. The computational device of claim 6 , wherein the computational operation is an addition-, subtraction-, multiplication-, or division-based operation.

15. The computational device of claim 6 , wherein the core is comprised in a neural network.

16. A non-transient computer readable medium that stores a set of instructions that is executable by a computational device to cause a core of the computational device to:

run, in parallel, a first and second pipeline of data from the memory of the core, wherein the first pipeline is configured to receive a first operand from the memory and the second pipeline is configured to receive a second operand from the memory, and wherein the first operand and the second operand are input operands for performing a computational operation and the first pipeline operates at least one cycle ahead of the second pipeline;

generate a memory address in the memory for the first operand;

read, on the first pipeline, the first operand from the generated memory address;

detect if the first operand is a special number, wherein a special number is a numerical value which yields a predictable operation result of the computational operation; and

store, in the memory, a result of the computational operation based on the detection whether the first operation is the special number.

17. The non-transient computer readable medium of claim 16 , wherein upon a detection that the first operand is a special number, the set of instructions is configured to cause the core of the computational device further to:

retrieve the result corresponding to the predictable operation result of the computational operation that is yielded by the detected special number; and

store the retrieved result in the memory for the first and second pipeline.

18. The non-transient computer readable medium of claim 17 , wherein the computational operation is a multiplication operation and wherein the first operand is detected as being a special number comprising a numerical value of zero, the set of instructions is configured to cause the core of the computational device to:

prevent a generation of a memory address for the second operand.

19. The non-transient computer readable medium of claim 17 , wherein the computational operation is a multiplication operation and wherein the first operand is detected as being a special number comprising a numerical value of one, the set of instructions is configured to cause the core of the computational device to:

generate a memory address for the second operand;

read, on the second pipeline, the second operand from the generated memory address; and

assign a value of the result as being equal to a value of the second operand.

20. The non-transient computer readable medium of claim 16 ,

wherein if the first operand is not a special number, the set of instructions is configured to cause the core of the computational device to:

generate a memory address in the memory for the second operand;

read, on the second pipeline, the second operand from the generated memory address;

perform the computational operation on the first and second operand; and

store the result of the performed operation in the memory for the first and second pipeline.

21. The computation device of claim 6 , wherein whether to receive, on the second pipeline, the second operand from the memory for performing the computational operation is determined depending on the detection of whether the first operand is the special number.