Methods and apparatus for a dual mode operational amplifier
Various embodiments of the present technology comprise a method and apparatus for a dual mode operational amplifier. According to various embodiments, the operational amplifier functions as both a fully-differential amplifier and a single-ended amplifier. The operational amplifier may comprise additional transistors that function as switches, which can be selectively operated according to a desired mode.
1. An operational amplifier, comprising:
a first sub-circuit connected to a supply voltage and a bias node, and comprising:
a first transistor connected in series with a second transistor;
a third transistor connected in series with the second transistor; and
a first node positioned between the second and third transistors;
a first mode switch configured to selectively connect the first node to the bias node;
a second sub-circuit connected to the first sub-circuit;
a third sub-circuit connected to:
the supply voltage; and
the bias node;
a fourth sub-circuit directly connected to the supply voltage; and
a second mode switch configured to selectively connect the fourth sub-circuit to the bias node;
wherein the operational amplifier operates in a fully-differential mode and a single-ended mode according to the first and second mode switches.
2. The operational amplifier according to claim 1 , wherein:
during the fully-differential mode, the first mode switch is OFF and the second mode switch is ON; and
during the single-ended mode, the first mode switch is ON and the second mode switch is OFF.
3. The operational amplifier according to claim 1 , wherein the fourth sub-circuit comprises:
a fourth transistor directly connected to the supply voltage;
a pair of transistors comprising a fifth transistor connected in parallel with a sixth transistor, wherein the pair of transistors is connected in series with the fourth transistor;
a current mirror circuit connected to the pair of transistors; and
a second node positioned between the fifth transistor and the current mirror circuit.
4. The operational amplifier according to claim 3 , wherein the second mode switch is connected to the bias node and the second node.
5. The operational amplifier according to claim 1 , wherein the first mode switch is responsive to a first mode signal and the second mode switch is responsive to a second mode signal.
6. The operational amplifier according to claim 5 , wherein the second mode signal is the inverse of the first mode signal.
7. The operational amplifier according to claim 5 , wherein each of the first and second mode signals comprise a low signal and a high signal.
8. The operational amplifier according to claim 7 , wherein the operational amplifier operates in a first mode when the first mode switch receives the low signal and the second mode switch receives the high signal.
9. The operational amplifier according to claim 8 , wherein the operational amplifier operates in a second mode when the first mode switch receives the high signal and the second mode switch receives the low signal.
10. The operational amplifier according to claim 9 , wherein:
the first mode comprises the fully-differential mode; and
the second mode comprises the single-ended mode.
11. A method for operating a dual mode operational amplifier, comprising:
receiving an input voltage at an input terminal of the operational amplifier, wherein the operational amplifier comprises:
a plurality of sub-circuits comprising: a first sub-circuit, a second sub-circuit, a third sub-circuit, and a fourth sub-circuit; and
a first mode switch and a second mode switch;
generating a mode signal, wherein:
the mode signal comprises a first mode signal and a second mode signal, and
the first mode signal corresponds to a fully-differential mode and the second mode signal corresponds to a single-ended mode;
supplying the mode signal to the operational amplifier; and
selectively connecting the fourth sub-circuit directly to the remaining sub-circuits from the plurality of sub-circuits via the second mode switch and according to the mode signal.
12. The method according to claim 11 , further comprising selectively operating a plurality of switches to perform a reset operation.
13. The method according to claim 11 , further comprising generating a first output voltage and a second output voltage with the operational amplifier according to the mode signal.
14. The method according to claim 11 , wherein the first mode signal applies a low voltage to the first mode switch and a high voltage to the second mode switch.
15. The method according to claim 11 , wherein the second mode signal applies a high voltage to the first mode switch and a low voltage to the second mode switch.
16. A system, comprising:
a sensor;
an operational amplifier connected to the sensor and configured to operate in a fully-differential mode and a single-ended mode and comprising:
a first sub-circuit connected to a supply voltage and a bias node, and comprising a first node, wherein the first sub-circuit outputs a first output voltage at the first node;
a first mode switch configured to selectively connect the first node to the bias node;
a second sub-circuit connected to the first sub-circuit;
a third sub-circuit connected to the supply voltage and the bias node, and comprising a second node, wherein the third sub-circuit outputs a second output voltage at the second node;
a fourth sub-circuit connected to the supply voltage; and
a second mode switch configured to selectively connect the fourth sub-circuit directly to the bias node;
an analog-to-digital converter configured to receive the second output voltage; and
a control circuit configured to generate a mode signal and transmit the mode signal to the operational amplifier, wherein the mode signal comprises:
a first mode signal that corresponds to the fully-differential mode; and
a second mode signal that corresponds to the single-ended mode.
17. The system according to claim 16 , wherein each of the first and second mode switches comprise an n-channel transistor comprising a gate terminal configured to receive the mode signal.
18. The system according to claim 16 , wherein the first mode signal results in:
the first mode switch receiving a low voltage; and
the second mode switch receiving a high voltage.
19. The system according to claim 16 , wherein the second mode signal results in:
the first mode switch receiving a high voltage; and
the second mode switch receiving a low voltage.
20. The system according to claim 16 , further comprising an inverter configured to receive the mode signal and generate a signal with an opposite logic level than that of the mode signal.