Transistor with multiple GaN-based alloy layers

1. A transistor, comprising:

a gallium nitride (GaN) layer;

a first GaN-based alloy layer having a top side and disposed on the GaN layer;

a second GaN-based alloy layer disposed on the first GaN-based alloy layer, wherein the second GaN-based alloy layer covers a first portion of the top side; and

a source contact structure, a drain contact structure, and a gate contact structure, wherein the source, drain, and gate contact structures are supported by the first GaN-based alloy layer, wherein the drain contact structure disposed on the second GaN-based alloy layer such that the drain contact structure is separated from the first GaN-based alloy layer by the second GaN-based alloy layer.

2. The transistor of claim 1 further comprising a third GaN-based alloy layer disposed on the first GaN based alloy layer, the third GaN-based alloy layer covers a second portion of the top side.

3. The transistor of claim 2 , wherein the drain contact structure forms an ohmic contact with the second GaN-based alloy layer, the source contact structure forms an ohmic contact with the third GaN-based alloy layer.

4. The transistor of claim 2 , wherein the first and second portions are of same lengths.

5. The transistor of claim 2 , wherein the first GaN-based alloy layer comprises Al(X1)In(Y1)Ga(1-X1-Y1)N, where X1 and Y1 are the concentrations of Aluminum and Indium, respectively, wherein the second GaN-based alloy layer comprises: Al(X2)In(Y2)Ga(1-X2-Y2)N, where X2 and Y2 are the concentrations of Aluminum and Indium, respectively, wherein the third GaN-based alloy layer comprises Al(X3)In(Y3)Ga(1-X3-Y3)N, where X3 and Y3 are the concentrations of Aluminum and Indium, respectively.

6. The transistor of claim 1 , wherein the drain contact structure forms an ohmic contact with the second GaN-based alloy layer, the source contact structure forms an ohmic contact with the first GaN-based alloy layer.

7. The transistor of claim 1 , wherein the second GaN-based alloy layer is at least partially positioned in a drain access region and contacts the drain contact structure.

8. A transistor, comprising:

a gallium nitride (GaN) layer;

a first GaN-based alloy layer having a top side and disposed on the GaN layer;

a second GaN-based alloy layer disposed on the first GaN-based alloy layer, wherein the second GaN-based alloy layer covers a first portion of the top side;

a source contact structure, a drain contact structure, and a gate contact structure, wherein the source, drain, and gate contact structures are supported by the first GaN-based alloy layer; and

a p-doped GaN layer positioned on the top side, wherein the gate contact structure is positioned on the p-doped GaN layer.

9. A transistor, comprising:

a gallium nitride (GaN) layer;

a first GaN-based alloy layer positioned on the GaN layer;

a second GaN-based alloy layer positioned on a first portion of the first GaN-based alloy layer, wherein a two-dimensional electron gas (2DEG) forms with different electron densities at an interface of the GaN layer and the first GaN-based alloy layer;

a source contact structure, a drain contact structure, and a gate contact structure, wherein the source, drain, and gate contact structures are supported by the first GaN-based alloy layer; and

a p-doped GaN layer positioned on a second portion of the first GaN-based alloy layer, wherein the gate contact structure is positioned on the p-doped GaN layer.

10. The transistor of claim 9 further comprising a third GaN-based alloy layer positioned on a third portion of the first GaN-based alloy layer, wherein the source contact structure contacts the third GaN-based alloy layer and the drain contact structure contacts the second GaN-based alloy layer.

11. The transistor of claim 10 , wherein the first GaN-based alloy layer comprises Al(X1)In(Y1)Ga(1-X1-Y1)N, where X1 and Y1 are the concentrations of Aluminum and Indium, respectively, wherein the second GaN-based alloy layer comprises: Al(X2)In(Y2)Ga(1-X2-Y2)N, where X2 and Y2 are the concentrations of Aluminum and Indium, respectively, wherein the third GaN-based alloy layer comprises Al(X3)In(Y3)Ga(1-X3-Y3)N, where X3 and Y3 are the concentrations of Aluminum and Indium, respectively.

12. A method, comprising:

providing a substrate including a gallium nitride (GaN) layer, a first GaN-based alloy layer disposed on the GaN layer and having a top side;

forming a second GaN-based alloy layer disposed on a first portion of the first GaN-based alloy layer; and

forming source, drain, and gate contact structures supported by the first GaN-based alloy layer, the drain contact structure being separated from the first GaN-based alloy layer by the second GaN-based alloy layer.

13. The method of claim 12 further comprising forming a third GaN-based alloy layer disposed on a second portion of the first GaN-based alloy layer.

14. The method of claim 12 , wherein the first GaN-based alloy layer comprises Al(X1)In(Y1)Ga(1-X1-Y1)N, where X1 and Y1 are the concentrations of Aluminum and Indium, respectively, wherein the second GaN-based alloy layer comprises: Al(X2)In(Y2)Ga(1-X2-Y2)N, where X2 and Y2 are the concentrations of Aluminum and Indium, respectively, wherein the third GaN-based alloy layer comprises Al(X3)In(Y3)Ga(1-X3-Y3)N, where X3 and Y3 are the concentrations of Aluminum and Indium, respectively.

15. A method, comprising:

providing a substrate including a gallium nitride (GaN) layer, a first GaN-based alloy layer disposed on the GaN layer and having a top side;

forming a second GaN-based alloy layer disposed on a first portion of the first GaN-based alloy layer;

forming source, drain, and gate contact structures supported by the first GaN-based alloy layer; and

forming a p-type GaN layer (pGaN) on the first GaN-based alloy layer, wherein the gate contact structure is positioned on the pGaN layer.

16. A method, comprising:

providing a substrate including a gallium nitride (GaN) layer, a first GaN-based alloy layer disposed on the GaN layer and having a top side;

forming a second GaN-based alloy layer disposed on a first portion and a second portion of the first GaN-based alloy layer but not on a third portion of the first GaN-based alloy layer; and

forming source, drain, and gate contact structures supported by the first GaN-based alloy layer, the source and drain contact structures contacting the second GaN-based alloy layer on the first and second portions, respectively, and the gate contact structure over the third portion of the first GaN-based alloy layer not contacting the second GaN-based alloy layer.

17. A transistor comprising:

a substrate including a gallium nitride (GaN) layer, a first GaN-based alloy layer disposed on the GaN layer and having a top side;

a second GaN-based alloy layer disposed on a first portion and a second portion of the first GaN-based alloy layer but not on a third portion of the first GaN-based alloy layer; and

source, drain, and gate contact structures supported by the first GaN-based alloy layer, the source and drain contact structures contacting the second GaN-based alloy layer on the first and second portions, respectively, and the gate contact structure over the third portion of the first GaN-based alloy layer not contacting the second GaN-based alloy layer.