Stacked field-effect transistors (FETs) with shared and non-shared gates
A semiconductor device includes a plurality of stacked gate regions spaced apart from each other on a substrate, a plurality of first epitaxial source/drain regions between the plurality of stacked gate regions, wherein the first epitaxial source/drain regions extend from sides of the plurality of stacked gate regions in a first doped region, a plurality of second epitaxial source/drain regions between the plurality of stacked gate regions and positioned over the first epitaxial source/drain regions, wherein the second epitaxial source/drain regions extend from sides of the plurality of stacked gate regions in a second doped region, and a contact region extending through a second epitaxial source/drain region of the plurality of second epitaxial source/drain regions to a first epitaxial source/drain region of the plurality of first epitaxial source/drain regions.
1. A semiconductor device, comprising:
a plurality of stacked gate regions spaced apart from each other on a substrate;
a plurality of first epitaxial source/drain regions between the plurality of stacked gate regions, wherein the first epitaxial source/drain regions are positioned on sides of the plurality of stacked gate regions in a first doped region;
a plurality of second epitaxial source/drain regions between the plurality of stacked gate regions and positioned over the first epitaxial source/drain regions, wherein the second epitaxial source/drain regions are positioned on sides of the plurality of stacked gate regions in a second doped region; and
a contact region extending through a second epitaxial source/drain region of the plurality of second epitaxial source/drain regions to a first epitaxial source/drain region of the plurality of first epitaxial source/drain regions.
2. The semiconductor device according to claim 1 , further comprising a contact region to another second epitaxial source/drain region of the plurality of second epitaxial source/drain regions which is stacked on and electrically isolated from a contact region to another first epitaxial source/drain region of the plurality of first epitaxial source/drain regions.
3. The semiconductor device according to claim 2 , further comprising a dielectric layer positioned between the contact region to the other second epitaxial source/drain region and the contact region to the other first epitaxial source/drain region.
4. The semiconductor device according to claim 1 , further comprising a plurality of dielectric layers respectively positioned between the plurality of first and second epitaxial source/drain regions.
5. The semiconductor device according to claim 4 , wherein the contact region extends through a dielectric layer of the plurality of dielectric layers to the first epitaxial source/drain region.
6. The semiconductor device according to claim 1 , wherein:
the plurality of first epitaxial source/drain regions are doped with a first type dopant; and
the plurality of second epitaxial source/drain regions are doped with a second type dopant different from the first type dopant.
7. The semiconductor device according to claim 1 , wherein a first portion of the plurality of stacked gate regions corresponds to the first doped region and a second portion of the plurality of stacked gate regions positioned over the first portion corresponds to the second doped region.
8. The semiconductor device according to claim 7 , wherein the first and second portions of the plurality of stacked gate regions comprise different materials from each other.
9. The semiconductor device according to claim 1 , wherein the plurality of stacked gate regions are alternately stacked with a plurality of semiconductor layers.
10. The semiconductor device according to claim 9 , wherein:
the plurality of first epitaxial source/drain regions extend from sides of the plurality of semiconductor layers in the first doped region; and
the plurality of second epitaxial source/drain regions extend from sides of the plurality of semiconductor layers in the second doped region.
11. A semiconductor device, comprising:
a plurality of gate regions spaced apart from each other on a substrate;
a plurality of first source/drain regions between the plurality of gate regions, wherein the plurality of first source/drain regions are doped with first-type dopant;
a plurality of second source/drain regions between the plurality of gate regions and positioned over the first source/drain regions, wherein the plurality of second source/drain regions are doped with a second-type dopant different from the first-type dopant; and
a plurality of dielectric layers respectively positioned between the plurality of first and second source/drain regions.
12. The semiconductor device according to claim 11 , further comprising a contact region extending through a second source/drain region of the plurality of second source/drain regions to a first source/drain region of the plurality of first source/drain regions.
13. The semiconductor device according to claim 12 , wherein the contact region extends through a dielectric layer of the plurality of dielectric layers to the first source/drain region.
14. The semiconductor device according to claim 11 , further comprising a contact region to a second source/drain region of the plurality of second source/drain regions which is stacked on and electrically isolated from a contact region to a first source/drain region of the plurality of first source/drain regions.
15. The semiconductor device according to claim 14 , further comprising a dielectric layer positioned between the contact region to the second source/drain region and the contact region to the first source/drain region.
16. The semiconductor device according to claim 11 , wherein the plurality of gate regions are alternately stacked with a plurality of semiconductor layers.
17. The semiconductor device according to claim 16 , wherein:
the plurality of first source/drain regions extend from sides of a first portion of the plurality of semiconductor layers; and
the plurality of second epitaxial source/drain regions extend from sides of a second portion of the plurality of semiconductor layers.
18. A semiconductor device, comprising:
a plurality of stacked gate regions spaced apart from each other on a substrate;
a plurality of source/drain regions between the plurality of stacked gate regions, wherein the source/drain regions are positioned on sides of the plurality of stacked gate regions in an active transistor region;
a plurality of dielectric layers between the plurality of stacked gate regions, wherein the plurality of dielectric layers are positioned on the plurality of source/drain regions in a dummy transistor region; and
a contact region extending through a dielectric layer of the plurality of dielectric layers to a source/drain region of the plurality of source/drain regions.
19. The semiconductor device according to claim 18 , wherein the plurality of stacked gate regions are alternately stacked with a plurality of semiconductor layers.
20. The semiconductor device according to claim 18 , wherein a plurality of spacers cover sides of the plurality of semiconductor layers in the dummy transistor region.