IP Library › Granted Patent US 11,048,571
Granted Patent B2
US 11,048,571 · App. 16/218,159 · Granted Jun 29, 2021

Selectively performing multi-plane read operations in non-volatile memory

Inventors: Nikolas Ioannou (Zurich, CH); Nikolaos Papandreou (Thalwil, CH); Roman A. Pletka (Uster, CH); Sasa Tomic (Kilchberg, CH); Charalampos Pozidis (Thalwil, CH); Aaron D. Fry (Richmond, TX); Timothy J. Fisher (Cypress, TX); Kevin E. Sallese (Plainfield, IL)
Assignee: International Business Machines Corporation
G06F11/076G06F3/064G06F3/0619G06F3/0688G06F12/0246G11C11/5642G11C29/021
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,048,571
App. No.
16/218,159
Granted
Jun 29, 2021
Kind
B2
Abstract

A computer-implemented method, according to one embodiment, includes: receiving a multi-page read request and predicting whether using a multi-plane read operation to read pages of storage space in memory which correspond to the multi-page read request will result in a bit error rate that is in a predetermined range. In response to predicting that using the multi-plane read operation to read the pages will not result in a bit error rate that is in the predetermined range, a threshold voltage shift (TVS) value is computed for the multi-plane read operation. Furthermore, the pages are read using the multi-plane read operation with the computed TVS. Other systems, methods, and computer program products are described in additional embodiments.

Claims (56)

1. A computer-implemented method, comprising:

receiving a multi-page read request;

predicting whether using a multi-plane read operation to read pages of storage space in memory which correspond to the multi-page read request will result in a bit error rate that is in a predetermined range;

in response to predicting that using the multi-plane read operation to read the pages will not result in a bit error rate that is in the predetermined range, computing a threshold voltage shift (TVS) value for the multi-plane read operation; and

reading the pages using the multi-plane read operation with the computed TVS,

wherein computing the TVS value includes:

determining whether any blocks of storage space in the memory which include the pages are experiencing transient effects, retention effects, or transient effects and retention effects,

in response to determining that a block is experiencing transient effects, retention effects, or transient effects and retention effects, computing the TVS value for a subset of the pages in the block experiencing transient effects, retention effects, or transient effects and retention effects,

in response to determining that none of the blocks are experiencing transient effects, retention effects, or transient effects and retention effects, computing a temporary TVS value for a subset of the pages in each respective block, and

combining the temporary TVS values to create the TVS value.

2. The computer-implemented method of claim 1 , comprising:

determining whether the multi-plane read operation was unable to read at least one of the pages; and

in response to determining that the multi-plane read operation was unable to read at least one of the pages, re-reading the at least one of the pages using a sequential read operation.

3. The computer-implemented method of claim 1 , comprising:

in response to predicting that using the multi-plane read operation to read the pages will result in a bit error rate that is in a predetermined range, examining blocks of storage space in the memory which include the pages;

determining whether two or more of the blocks are experiencing transient effects, retention effects, or transient effects and retention effects; and

in response to determining that fewer than two of the blocks are experiencing transient effects, retention effects, or transient effects and retention effects, computing the TVS value.

4. The computer-implemented method of claim 3 , comprising:

in response to determining that two or more of the blocks are experiencing transient effects, retention effects, or transient effects and retention effects, reading the pages using a sequential read operation.

5. The computer-implemented method of claim 1 , wherein the TVS value is an average of the temporary TVS values.

6. The computer-implemented method of claim 1 , wherein the TVS value is a median of the temporary TVS values.

7. The computer-implemented method of claim 1 , wherein the memory includes three-dimensional triple-level cell NAND Flash.

8. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions readable, executable, or readable and executable by a processor to cause the processor to:

receive, by the processor, a multi-page read request;

predict, by the processor, whether using a multi-plane read operation to read pages of storage space in memory which correspond to the multi-page read request will result in a bit error rate that is in a predetermined range;

in response to predicting that using the multi-plane read operation to read the pages will not result in a bit error rate that is in the predetermined range, compute, by the processor, a threshold voltage shift (TVS) value for the multi-plane read operation; and

read, by the processor, the pages using the multi-plane read operation with the computed TVS,

wherein computing the TVS value includes:

determining whether any blocks of storage space in the memory which include the pages are experiencing transient effects, retention effects, or transient effects and retention effects;

in response to determining that a block is experiencing transient effects, retention effects, or transient effects and retention effects, computing the TVS value for a subset of the pages in the block experiencing transient effects, retention effects, or transient effects and retention effects;

in response to determining that none of the blocks are experiencing transient effects, retention effects, or transient effects and retention effects, compute, by the processor, a temporary TVS value for a subset of the pages in each respective block; and

combine, by the processor, the temporary TVS values to create the TVS value.

9. The computer program product of claim 8 , the program instructions readable, executable, or readable and executable by the processor to cause the processor to:

determine, by the processor, whether the multi-plane read operation was unable to read at least one of the pages; and

in response to determining that the multi-plane read operation was unable to read at least one of the pages, re-read, by the processor, the at least one of the pages using a sequential read operation.

10. The computer program product of claim 8 , the program instructions readable executable, or readable and executable by the processor to cause the processor to:

in response to predicting that using the multi-plane read operation to read the pages will result in a bit error rate that is in a predetermined range, examine, by the processor, blocks of storage space in the memory which include the pages;

determine, by the processor, whether two or more of the blocks are experiencing transient effects, retention effects, or transient effects and retention effects; and

in response to determining that fewer than two of the blocks are experiencing transient effects, retention effects, or transient effects and retention effects, compute, by the processor, the TVS value.

11. The computer program product of claim 10 , the program instructions readable, or executable, or readable and executable by the processor to cause the processor to:

in response to determining that two or more of the blocks are experiencing transient effects, retention effects, or transient effects and retention effects, read, by the processor, the pages using a sequential read operation.

12. The computer program product of claim 8 , wherein the TVS value is an average of the temporary TVS values.

13. The computer program product of claim 8 , wherein the TVS value is a median of the temporary TVS values.

14. A system, comprising:

a processor; and

logic integrated with, executable by, or integrated with and executable by the processor, the logic being configured to:

receive, by the processor, a multi-page read request;

predict, by the processor, whether using a multi-plane read operation to read pages of storage space in memory which correspond to the multi-page read request will result in a bit error rate that is in a predetermined range;

in response to predicting that using the multi-plane read operation to read the pages will not result in a bit error rate that is in the predetermined range, compute, by the processor, a threshold voltage shift (TVS) value for the multi-plane read operation; and

read, by the processor, the pages using the multi-plane read operation with the computed TVS,

wherein computing the TVS value includes:

determining whether any blocks of storage space in the memory which include the pages are experiencing transient effects, retention effects, or transient effects and retention effects,

in response to determining that a block is experiencing transient effects, retention effects, or transient effects and retention effects, computing the TVS value for a subset of the pages in the block experiencing transient effects, retention effects, or transient effects and retention effects,

in response to determining that none of the blocks are experiencing transient effects, retention effects, or transient effects and retention effects, computing a temporary TVS value for a subset of the pages in each respective block, and

combining the temporary TVS values to create the TVS value.

15. The system of claim 14 , wherein the memory includes three-dimensional triple-level cell NAND Flash.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2019
From: IOANNOU, NIKOLAS; PAPANDREOU, NIKOLAOS; PLETKA, ROMAN A.; TOMIC, SASA; POZIDIS, CHARALAMPOS; FRY, AARON D.; FISHER, TIMOTHY J.; SALLESE, KEVIN E.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 049648/0614 →
Continuity (1)
Related Publication 20200192735A1 · Jun 18, 2020
Cited By (1)
US 12,743,386