Background calibration of non-linearity of samplers and amplifiers in ADCs
Analog circuits are often non-linear, and the non-linearities can hurt performance. Designers would trade off power consumption to achieve better linearity. An efficient and effective calibration technique can address the non-linearities and reduce the overall power consumption. A dither signal injected to the analog circuit can be used to expose the non-linear behavior in the digital domain. To detect the non-linearities, a counting approach is applied to isolate non-linearities independent of the input distribution. The approach is superior to and different from other approaches in many ways.
1. A calibration system with efficient error estimation, comprising:
dither circuitry to inject a dither at an input of a circuit and to remove the dither at an output of the circuit;
counting circuitry to count a first number of samples of the output corresponding to a first value of the dither falling within a range defined by an inspection point of the output, and count a second number of samples of the output corresponding to a second, different value of the dither falling within the range defined by the inspection point of the output;
error circuitry to compare the first number and the second number, and determine an error estimate based on the comparison; and
calibration circuitry to drive the error estimate towards zero.
2. The calibration system of claim 1 , wherein the dither is a signal having a plurality of values randomly distributed between the plurality of values.
3. The calibration system of claim 1 , wherein the circuit comprises one or more of the following: a buffer, a track and hold circuit, and an amplifier.
4. The calibration system of claim 1 , wherein the inspection point comprises one of the following: a positive value, a positive dither value, a negative value, a negative dither value, and zero.
5. The calibration system of claim 1 , wherein the range defined by the inspection point includes one of the following: a range of outputs below a first inspection point, and a range of outputs above a second inspection point.
6. The calibration system of claim 1 , wherein the inspection points changes randomly to accommodate different input conditions.
7. The calibration system of claim 1 , wherein the inspection points changes based on one or more conditions of the input of the circuit.
8. The calibration system of claim 1 , wherein the error circuitry comprises:
subtraction circuitry to subtract the first number and the second number to form a partial error at the inspection point.
9. The calibration system of claim 1 , wherein the error circuitry determines the error estimate by adding partial errors determined at the inspection point and a different inspection point.
10. The calibration system of claim 1 , wherein the error circuitry determines the error estimate by subtracting partial errors determined at the inspection point and a different inspection point.
11. The calibration system of claim 1 , wherein the calibration circuitry updates an estimate for a component of the circuit based on the error estimate and a least means squared update equation.
12. The calibration system of claim 11 , wherein the calibration circuitry corrects the output of the circuit based on the estimate for the component of the circuit.
13. A method for efficient error estimation and calibration of a circuit, comprising:
adding a dither at an input of the circuit;
removing the dither at an output of the circuit;
counting a first number of samples of the output corresponding to a first value of the dither falling within a range defined by an inspection point of the output, and
counting a second number of samples of the output corresponding to a second, different value of the dither falling within the range defined by the inspection point of the output;
comparing the first number and the second number;
determining an error estimate based on the comparison; and
driving the error estimate towards zero.
14. The method of claim 13 , wherein driving the error estimate towards zero comprises:
updating an estimate of a component of the circuit based on the error estimate; and
correcting a digital output of the circuit based on the estimate.
15. The method of claim 14 , wherein driving the error estimate to zero comprises:
updating the estimate of the component of the circuit based on a parameter that enhances even symmetrical errors while attenuating odd symmetrical errors.
16. The method of claim 14 , wherein driving the error estimate to zero comprises:
updating the estimate of the component of the circuit based on a parameter that enhances odd symmetrical errors while attenuating even symmetrical errors.
17. The method of claim 13 , wherein:
the comparison forms a partial error estimate at the inspection point; and
determining the error estimate comprises combining partial error estimates determined at the inspection points and a different inspection point.
18. An apparatus for estimating errors and calibrating a circuit, comprising:
means for injecting a dither at an input of a circuit and removing the dither at an output of the circuit;
means for evaluating a first count of the output of the circuit associated with a first value of the dither falling within a ranges defined by an inspection point, and a second count of the output of the circuit of the circuit associated with a second value of the dither falling within the range defined by the inspection point;
means for combining the first count and the second count to expose an error associated with a component of the circuit; and
means for updating an estimate of the component of the circuit based on the error.
19. The apparatus of claim 18 , wherein the means for evaluating the first count and the second count comprises means for counting a number of samples of the output of the circuit falling within the ranges defined by the inspection point.
20. The apparatus of claim 18 , further comprising:
means for digitally correcting the output of the circuit based on the estimate of the component and a model for the component of the circuit.