Recovering data from a faulty memory block in a memory system

1. A method for recovering data from a faulty memory block in a memory system, the method comprising:

reading a target word line in a memory block to obtain a first data;

determining the first data has an uncorrectable error; and then

adjusting bias parameters of a first group of neighboring word lines within the memory block, wherein adjusting bias parameters creates first adjusted bias parameters; and

reading the target word line using the adjusted bias parameters to obtain second data from the target word line.

2. The method of claim 1 , wherein adjusting the bias parameters of the first group of neighboring word lines further comprises:

adjusting a read pass voltage of a first word line disposed immediately adjacent to the target word line, and the first word line disposed between a second word line and the target word line; and

adjusting a read pass voltage of the second word line.

3. The method of claim 1 , further comprising:

determining the second data has a second uncorrectable error; and then

adjusting bias parameters of a second group of lines within the memory block, wherein adjusting the bias parameters of the second group creates second adjusted bias parameters; and

reading the target word line using the first and second adjusted bias parameters to obtain a third data from the target word line.

4. The method of claim 3 , wherein adjusting the bias parameters of the second group of lines further comprises adjusting a select voltage of a select line of the memory block, wherein the select line is coupled to a select gate of the memory block.

5. The method of claim 4 , wherein adjusting the bias parameters of the second group of lines further comprises adjusting a read pass voltage of a dummy word line within the memory block, wherein the dummy word line is disposed along a periphery of the memory block.

6. The method of claim 3 , wherein adjusting the bias parameters of the second group of lines further comprises adjusting a read pass voltage of a dummy word line within the memory block, wherein the dummy word line is disposed along a periphery of the memory block.

7. The method of claim 3 , wherein adjusting the bias parameters of the second group of lines comprises increasing an amount of voltage applied to the second group by a predetermined threshold amount.

8. The method of claim 1 , wherein adjusting the bias parameters of the first group of neighboring word lines further comprises: increasing a first read pass voltage and a second read pass voltage by a predetermined amount, the first read pass voltage is applied to a first word line disposed immediately adjacent to the target word line and the first word line disposed between a second word line and the target word line, and the second read pass voltage is applied to the second word line during the read operation.

9. The method of claim 1 , wherein determining the first data has an uncorrectable error further comprises:

determining the first data has a decoding failure;

executing a read error handling routine on the first data; and

determining the read error handling routine was unsuccessful in recovering the first data.

10. A memory controller, comprising:

a first terminal coupled to a memory block;

processing circuitry coupled to the first terminal; and

a memory coupled to the processing circuitry, the memory storing computer-readable instructions that when executed by the processing circuitry, cause the memory controller to:

receive a first data and a first address of the first data, wherein the first address defines a target word line corresponding to a memory cell in the memory block;

determine the first data has an uncorrectable error; and then

adjust first bias parameters of a first group of neighboring word lines within the memory block by a predetermined threshold; the adjusting creates first adjusted bias parameters, wherein the first group of neighboring word lines comprises a first word line immediately adjacent to the target word line;

read the target word line using the first adjusted bias parameters; and

receive a second data from the first address.

11. The memory controller of claim 10 , wherein when the instructions cause the memory controller to adjust the first bias parameters, the instructions further cause the memory controller to increase a read pass voltage of the first word line by the predetermined threshold.

12. The memory controller of claim 10 , wherein the predetermined threshold is between 0.5 mV and 2 V.

13. The memory controller of claim 10 , wherein the computer-readable instructions further cause the memory controller to:

determine the second data has a second uncorrectable error; and then

adjust second bias parameters of a second group of lines within the memory block by a second predetermined threshold, the adjusting creates second adjusted bias parameters;

read the target word line using the first and second adjusted bias parameters; and

receive a third data from the first address.

14. The memory controller of claim 13 , wherein when the instructions cause the memory controller to adjust the second bias parameters, the instructions further cause the memory controller to:

increase a select voltage of a select line of the memory block; and

increase a read pass voltage of a dummy word line of the memory block.

15. The memory controller of claim 14 , wherein when the instructions cause the memory controller to adjust the second bias parameters, the instructions further cause the memory controller to increase a second select voltage of a second select line of the memory block.

16. The memory controller of claim 13 further comprising a read parameter adjustment module, wherein the memory controller adjusts the first and second bias parameters by way of the read parameter adjustment module.