Chip package with fan-out structure
A chip package is provided. The chip package includes a semiconductor die and a protection layer surrounding the semiconductor die. The chip package also includes a dielectric layer over the semiconductor die and the protection layer. The dielectric layer has an upper surface with cutting scratches. The chip package further includes a conductive layer over the dielectric layer and filling some of the cutting scratches.
1. A chip package, comprising:
a semiconductor die;
a protection layer surrounding the semiconductor die;
a dielectric layer over the semiconductor die and the protection layer, wherein the dielectric layer has an upper surface with cutting scratches, wherein bottoms of the cutting scratches are positioned at height levels that are lower than a topmost surface of the dielectric layer and higher than a topmost surface of the semiconductor die; and
a conductive layer over the dielectric layer and filling some of the cutting scratches.
2. The chip package as claimed in claim 1 , further comprising a conductive structure in the protection layer and separated from the semiconductor die by a portion of the protection layer, wherein the protection layer has a recessed portion between the semiconductor die and the conductive structure.
3. The chip package as claimed in claim 2 , wherein the dielectric layer fills the recessed portion of the protection layer.
4. The chip package as claimed in claim 2 , wherein a top surface of the conductive structure is between the topmost surface of the dielectric layer and a bottommost surface of the dielectric layer.
5. The chip package as claimed in claim 1 , wherein an interface between the conductive layer and the dielectric layer has an undulate morphology.
6. The chip package as claimed in claim 1 , wherein widths of the cutting scratches are substantially the same.
7. The chip package as claimed in claim 1 , wherein each of the cutting scratches has a width in a range from about 20 μm to about 60 μm, and each of the cutting scratches has a depth in a range from about 0.05 μm to about 0.1 μm.
8. The chip package as claimed in claim 1 , further comprising a second dielectric layer over the dielectric layer, wherein the second dielectric layer fills some of the scratches that are not filled with the conductive layer.
9. The chip package as claimed in claim 1 , wherein intervals between the cutting scratches are substantially the same.
10. The chip package as claimed in claim 1 , wherein the conductive layer is in direct contact with sidewalls of some of the cutting scratches.
11. A chip package, comprising:
a semiconductor die;
a protection layer surrounding the semiconductor die;
a dielectric layer over the semiconductor die and the protection layer; and
a conductive layer over the dielectric layer, wherein the conductive layer has a plurality of protruding portions extending into the dielectric layer, and bottoms of the protruding portions are positioned at height levels that are lower than a topmost surface of the dielectric layer and higher than a topmost surface of the semiconductor die.
12. The chip package as claimed in claim 11 , wherein widths of the protruding portions of the conductive layer are substantially the same.
13. The chip package as claimed in claim 11 , wherein each of the protruding portions of the conductive layer has a width in a range from about 20 μm to about 60 μm, and each of the protruding portions of the conductive layer has a height in a range from about 0.05 μm to about 0.1 μm.
14. The chip package as claimed in claim 11 , further comprising a second dielectric layer over the dielectric layer, wherein the second dielectric layer has a plurality of second protruding portions extending into the dielectric layer.
15. The chip package as claimed in claim 14 , wherein a width of each of the protruding portions of the conductive layer is substantially equal to a width of each of the protruding portions of the second dielectric layer.
16. A chip package, comprising:
a semiconductor die;
a protection layer surrounding the semiconductor die;
a dielectric layer over the semiconductor die and the protection layer; and
a conductive layer over the dielectric layer, wherein an interface between the conductive layer and the dielectric layer has an undulate morphology, and bottoms of the interface with the undulated morphology are positioned at height levels that are lower than a topmost surface of the dielectric layer and higher than a topmost surface of the semiconductor die.
17. The chip package as claimed in claim 16 , further comprising a second dielectric layer over the dielectric layer and the conductive layer, wherein an interface between the second dielectric layer and the dielectric layer has a second undulate morphology.
18. The chip package as claimed in claim 17 , wherein the undulate morphology and the second undulate morphology are substantially the same.
19. The chip package as claimed in claim 16 , further comprising a conductive structure in the protection layer and separated from the semiconductor die by a portion of the protection layer, wherein the protection layer has a recessed portion between the semiconductor die and the conductive structure.
20. The chip package as claimed in claim 16 , further comprising a conductive structure in the protection layer and separated from the semiconductor die by a portion of the protection layer, wherein a top surface of the conductive structure is between the topmost surface of the dielectric layer and a bottommost surface of the dielectric layer.