IP Library › Granted Patent US 11,610,971
Granted Patent B2
US 11,610,971 · App. 16/222,976 · Granted Mar 21, 2023

Cap layer on a polarization layer to preserve channel sheet resistance

Inventors: Sansaptak Dasgupta (Hillsboro, OR); Marko Radosavljevic (Portland, OR); Han Wui Then (Portland, OR); Nidhi Nidhi (Hillsboro, OR); Rahul Ramaswamy (Portland, OR); Johann Rode (Hillsboro, OR); Paul Fischer (Portland, OR); Walid Hafez (Portland, OR)
Assignee: Intel Corporation
H01L29/205H01L21/0217H01L21/0254H01L21/02458H01L21/76224H01L29/0847H01L29/1033H01L29/2003H01L29/207H01L29/4236H01L29/42376H01L29/66462H01L29/7787
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Quick Facts
Patent No.
US 11,610,971
App. No.
16/222,976
Granted
Mar 21, 2023
Kind
B2
Abstract

An integrated circuit structure comprises a base layer that includes a channel region, wherein the base layer and the channel region include group III-V semiconductor material. A polarization layer stack is over the base layer, wherein the polarization layer stack comprises a buffer stack, an interlayer over the buffer stack, a polarization layer over the interlayer. A cap layer stack is over the polarization layer to reduce transistor access resistance.

Claims (35)

1. An integrated circuit structure, comprising:

a base layer that includes a channel region, wherein the base layer and the channel region include group III-V semiconductor material;

a polarization layer stack over the base layer; and

a cap layer stack over the polarization layer stack, wherein the cap layer stack comprises a nitride compound of silicon, gallium, aluminum, or boron, and does not fill pits and defects of a top surface of the polarization layer stack.

2. The integrated circuit structure of claim 1 , wherein the cap layer stack comprises at least one of SiNx, GaN, AIN, and BN.

3. The integrated circuit structure of claim 1 , wherein the cap layer stack comprises a first cap layer made of a III-N material, and a second cap layer comprising a dielectric.

4. The integrated circuit structure of claim 3 , wherein the first cap layer is doped with a Si dopant.

5. The integrated circuit structure of claim 1 , wherein the cap layer stack has a thickness range of approximately 1-20 nm.

6. The integrated circuit structure of claim 1 , wherein the polarization layer stack comprises a buffer stack, an interlayer over the buffer stack, and a polarization layer over the interlayer.

7. The integrated circuit structure of claim 6 , wherein the buffer stack of the polarization layer stack comprises gallium and nitrogen, and the interlayer and the polarization layer of the polarization layer stack comprise aluminum and nitrogen.

8. The integrated circuit structure of claim 1 , wherein the base layer and the channel region comprise gallium and nitrogen.

9. The integrated circuit structure of claim 1 , wherein the cap layer stack reduces channel sheet resistance.

10. A transistor, comprising:

a base layer that includes a channel region, wherein the base layer and the channel region comprise gallium and nitride;

a polarization layer stack over the base layer;

a gate electrode over the polarization layer stack; and

source and drain regions adjacent to the channel region,

wherein the polarization layer stack comprises a buffer stack, an interlayer over the buffer stack, a polarization layer over the interlayer, and a cap layer stack over the polarization layer, wherein the cap layer stack comprises a nitride compound of silicon, gallium, aluminum, or boron, and does not fill pits and defects of a top surface of the polarization layer stack.

11. The transistor of claim 10 , wherein the cap layer stack comprises at least one of SiNx, GaN, AIN, and BN.

12. The transistor of claim 10 , wherein the cap layer stack comprises a first cap layer made of a III-N material, and a second cap layer comprises a dielectric.

13. The transistor of claim 12 , wherein the first cap layer is doped with a Si dopant.

14. The transistor of claim 10 , wherein the cap layer stack has a thickness range of approximately 1-20 nm.

15. The transistor of claim 10 , wherein the buffer stack of the polarization layer stack comprises gallium and nitrogen.

16. The transistor of claim 10 , wherein the interlayer and the polarization layer of the polarization layer stack comprise aluminum and nitrogen.

17. The transistor of claim 10 , wherein the cap layer stack reduces channel sheet resistance.

18. An integrated circuit structure, comprising:

a base layer that includes a channel region, wherein the base layer and the channel region include group III-V semiconductor material;

a polarization layer stack over the base layer; and

a cap layer stack is conformal with the polarization layer stack, wherein wherein the cap layer stack comprises a nitride compound of silicon, gallium, aluminum, or boron, and fills pits and defects of a top surface of the polarization layer stack.

19. A transistor, comprising:

a base layer that includes a channel region, wherein the base layer and the channel region comprise gallium and nitride;

a polarization layer stack over the base layer;

a gate electrode over the polarization layer stack; and

source and drain regions adjacent to the channel region,

wherein the polarization layer stack comprises a buffer stack, an interlayer over the buffer stack, a polarization layer over the interlayer, and a cap layer stack over the polarization layer, wherein the cap layer stack comprises a nitride compound of silicon, gallium, aluminum, or boron, and fills pits and defects of a top surface of the polarization layer stack.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 15, 2019
From: DASGUPTA, SANSAPTAK; RADOSAVLJEVIC, MARKO; THEN, HAN WUI; NIDHI, NIDHI; RAMASWAMY, RAHUL; RODE, JOHANN; FISCHER, PAUL; HAFEZ, WALID
To: INTEL CORPORATION
Reel/Frame 051027/0125 →
Continuity (1)
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