IP Library Granted Patent US 10,638,599
Granted Patent B2
US 10,638,599 · App. 16/223,195 · Granted Apr 28, 2020

Backplane footprint for high speed, high density electrical connectors

Inventors: Marc Robert Charbonneau (Bedford, NH); Jose Ricardo Paniagua (Newmarket, NH)
Assignee: Amphenol Corporation
H05K1/0225H05K1/0219H05K1/0251H05K1/115H05K3/429H05K2201/0723H05K2201/096H05K2201/09727H05K2201/09845
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Quick Facts
Patent No.
US 10,638,599
App. No.
16/223,195
Granted
Apr 28, 2020
Kind
B2
Abstract

A printed circuit board includes a plurality of layers including conductive layers separated by dielectric layers, the conductive layers including a signal layer; and via patterns formed in the plurality of layers, each of the via patterns comprising first and second signal vias extending from a first surface of the printed circuit board to the signal layer, the signal layer including first and second signal traces connected to the first and second signal vias, respectively, the signal layer further including a ground conductor located between the signal traces and adjacent signal-carrying elements.

Claims (9)

1. A printed circuit board comprising:

a plurality of layers including conductive layers separated by dielectric layers, the conductive layers including at least one signal layer; and

via patterns formed in the plurality of layers within a connector footprint of the printed circuit board, the via patterns including a first via pattern and a second via pattern,

wherein the signal layer includes a conductor located between the first via pattern and the second via pattern and configured for connection to a reference voltage, wherein the signal layer includes at least one signal trace between the first and second via patterns and wherein the conductor is located between the at least one signal trace and the first via pattern.

2. The printed circuit board as defined in claim 1 , wherein the via patterns include first and second columns of via patterns and wherein the conductor is located between the first and second columns of via patterns.

3. The printed circuit board as defined in claim 1 , wherein the conductor comprises a conductive strip located between the first and second via patterns.

4. The printed circuit board as defined in claim 1 , wherein the conductor surrounds the first and second via patterns.

5. The printed circuit board as defined in claim 1 , wherein the conductor includes a plurality of conductors configured for connection to the reference voltage.

6. The printed circuit board as defined in claim 1 , wherein the ground conductor comprises a copper conductor configured for connection to ground.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2019
From: CHARBONNEAU, MARC ROBERT; PANIAGUA, JOSE RICARDO
To: AMPHENOL CORPORATION
Reel/Frame 048001/0005 →
Continuity (4)
Division 15807444 · Nov 8, 2017
Continuation In Part 15452096 · Mar 7, 2017
Provisional Application 62305049 · Mar 8, 2016
Related Publication 20190150273A1 · May 16, 2019
Cited By (5)
US 1,067,191 US 1,068,685 US 12,207,395 US 12,309,915 US 12,444,863