Steering tag support in virtualized environments
A method of managing memory access includes receiving, at an input output memory management unit, a memory access request from a device. The memory access request includes a virtual steering tag associate associated with a virtual machine. The method further includes translating the virtual steering tag to a physical steering tag directing memory access of a cache memory associated with a processor core of a plurality of processor cores. The virtual machine is implemented on the processor core. The method also includes accessing the cache memory to implement the memory access request.
1. A method of managing memory access, the method comprising:
receiving, at an input output memory management unit, a memory access request from a device, the memory access request including a memory address and a virtual steering tag associated with a virtual machine, the virtual steering tag different from the memory address;
translating the virtual steering tag to a physical steering tag directing cache injection memory access of a cache memory associated with a processor core of a plurality of processor cores, the virtual machine implemented on the processor core; and
accessing the cache memory to implement the memory access request based on the memory address.
2. The method of claim 1 , wherein translating the virtual steering tag includes translation with the input output memory management unit.
3. The method of claim 1 , wherein translating the virtual steering tag includes accessing a tag map.
4. The method of claim 3 , further comprising:
assigning the virtual steering tag, wherein the virtual steering tag is assigned by a hypervisor managing the virtual machine; and
generating an entry in the tag map associating the virtual steering tag with the physical steering tag.
5. The method of claim 4 , further comprising:
implementing, with the hypervisor, the virtual machine on a second processor core of the plurality of processor cores; and
updating the tag map to associate the virtual steering tag with a second physical steering tag directing memory access of a cache memory associated with the second processor core.
6. The method of claim 5 , further comprising:
implementing, with the hypervisor, a second virtual machine on the processor core of the plurality of processor cores; and
assigning, with the hypervisor, a second virtual steering tag to the second virtual machine.
7. The method of claim 4 , further comprising providing the virtual steering tag to the device.
8. The method of claim 4 , wherein the virtual steering tag is assigned based on the virtual machine.
9. The method of claim 1 , wherein memory access to the cache memory of the processor core of the plurality of processor cores is managed by a memory controller.
10. The method of claim 9 , wherein the processor core includes an associated translation lookaside buffer, wherein the memory access request further includes a virtual address, the method further comprising translating the virtual address.
11. A method of managing memory access to a virtual machine implemented on a processor core of a plurality of processor cores, the method comprising:
instantiating with a hypervisor a virtual machine on a first processor core of a plurality of processor cores;
recording an entry into a tag map, the entry pairing a physical steering tag associated with the first processor core and a virtual steering tag associated with the virtual machine, the tag map accessible by an input output memory management unit associated with the plurality of processor cores; and
providing the virtual steering tag to a device having access to the input output memory management unit.
12. The method of claim 11 , further comprising:
moving the virtual machine from the first processor core to a second processor core of the plurality of processor cores; and
in response to the moving, recording a second entry in the tag map, the second entry pairing a second physical steering tag with the virtual steering tag.
13. The method of claim 12 , further comprising removing the entry.
14. The method of claim 11 , further comprising:
receiving, at the input output memory management unit, a memory access request from the device, the memory access request including the virtual steering tag;
translating the virtual steering tag to the physical steering tag directing cache injection memory access of a cache memory associated with the first processor core; and
accessing the cache memory to implement the memory access request.
15. The method of claim 14 , wherein the cache memory is uniquely dedicated for use by the first processor core.
16. The method of claim 14 , wherein the virtual steering tag is assigned based on the virtual machine.
17. The method of claim 14 , wherein the cache memory is a level 1 processor cache.
18. A system comprising:
a plurality of processor cores, each processor core having a dedicated cache memory;
a memory controller to access the dedicated cache memory;
an input-output memory management unit in communication with the memory controller, the input-output memory management unit having access to a tag map associating a virtual steering tag with a physical steering tag; and
a device in communication with the input-output memory management unit, the device to provide a memory access request to the input-output memory management unit, the memory access request including a virtual steering tag and a memory address different from the virtual steering tag, the input-output memory management unit to translate the virtual steering tag to a physical steering tag associated with the dedicated cache memory of each of the plurality of processor cores.
19. The system of claim 18 , further comprising a physical tag map associating the physical steering tag with the dedicated cache memory.
20. The system of claim 18 , further comprising a translation lookaside buffer, the memory access request including a virtual address, the translation lookaside buffer to translate the virtual address to a physical address in the dedicated cache memory.