Fan-out package structure and method

1. A method comprising:

embedding a semiconductor structure in a molding compound layer;

depositing a plurality of photo-sensitive material layers over the molding compound layer, the plurality of photo-sensitive material layers comprising a second photo-sensitive material layer over a first photo-sensitive material layer;

developing the plurality of photo-sensitive material layers to form a plurality of openings, wherein the first photo-sensitive material layer is exposed to light prior to depositing the second photo-sensitive material layer, the first photo-sensitive material layer being developed after depositing the second photo-sensitive material layer, wherein a first portion and a second portion of an opening of the plurality of openings are formed in the first and second photo-sensitive material layers respectively; and

filling the first portion and the second portion of the opening with a conductive material to form a first via in the first portion and a first redistribution layer in the second portion.

2. The method of claim 1 , wherein the step of embedding the semiconductor structure in the molding compound layer comprises:

attaching the semiconductor structure on a carrier; and

depositing the molding compound layer over the carrier.

3. The method of claim 1 , wherein the step of depositing the plurality of photo-sensitive material layers over the molding compound layer comprises:

depositing a first photo-sensitive material layer on the molding compound layer;

exposing the first photo-sensitive material layer to light according to a first pattern;

depositing a second photo-sensitive material layer on the first photo-sensitive material layer; and

exposing the second photo-sensitive material layer to light according to a second pattern, wherein the first pattern and the second pattern are different.

4. The method of claim 3 , wherein:

the first portion of the opening is formed in the first photo-sensitive material layer and based upon the first pattern; and

the second portion of the opening is formed in the second photo-sensitive material layer and based upon the second pattern.

5. The method of claim 1 , wherein:

the first portion is a via portion; and

the second portion is a metal line portion, and wherein a width of the second portion is greater than a width of the first portion.

6. The method of claim 1 , further comprising:

forming a second via and a second redistribution layer over the first via and the first redistribution layer, wherein a center point of the second via is vertically aligned with a center portion of the first via.

7. The method of claim 6 , further comprising:

forming a third via and a third redistribution layer over the second via and the second redistribution layer, wherein the center point of the second via is vertically aligned with a center portion of the third via.

8. The method of claim 1 , further comprising:

prior to the step of filling the first portion and the second portion of the opening with the conductive material, forming a photoresist layer over the plurality of photo-sensitive material layers.

9. The method of claim 8 , wherein:

a sidewall of the photoresist layer is vertically aligned with a sidewall of the plurality of openings.

10. The method of claim 1 , wherein:

a seed layer is formed on a bottom and sidewalls of the first opening.

11. A method comprising:

embedding a semiconductor structure in a molding compound layer;

depositing a first plurality of photo-sensitive material layers over the molding compound layer, the first plurality of photo-sensitive material layers comprising a second photo-sensitive material layer on top of a first photo-sensitive material layer;

developing the first plurality of photo-sensitive material layers to form a first opening wherein the first photo-sensitive material layer is exposed to light prior to depositing the second photo-sensitive material layer, the first photo-sensitive material layer being developed after depositing the second photo-sensitive material layer;

filling the first opening with a conductive material to form a first interconnect structure;

developing a second plurality of photo-sensitive material layers to form a second opening; and

filling the second opening with the conductive material to form a second interconnect structure, wherein edges of the second interconnect structure are vertically aligned with edges of the first interconnect structure.

12. The method of claim 11 , wherein:

the semiconductor structure comprises a connector in direct contact with the first interconnect structure.

13. The method of claim 11 , further comprising:

forming a bump over the second interconnect structure.

14. The method of claim 13 , wherein:

an outermost edge of the bump is vertically aligned with an outermost edge of the second interconnect structure.

15. The method of claim 11 , wherein filling of the first and the second openings with the conductive material comprises:

using a plating process, wherein the conductive material grows from bottoms as well as sidewalls of the first and the second openings as a result of the plating process.

16. A method comprising:

embedding a semiconductor structure in a molding compound layer;

exposing a top surface of the semiconductor structure through a grinding process;

depositing a first plurality of photo-sensitive material layers over the molding compound layer, the first plurality of photo-sensitive material layers comprising a second photo-sensitive material layer over a first photo-sensitive material layer;

developing the first plurality of photo-sensitive material layers to form a first opening, wherein prior to developing the first or the second photo-sensitive material layers, the first photo-sensitive material layer is exposed to light according to a first pattern and the second photo-sensitive material layer is exposed to light according to a second pattern, the first pattern is different than the second pattern;

filling the first opening with a conductive material to form a first interconnect structure;

developing a second plurality of photo-sensitive material layers to form a second opening, wherein at least one edge of the second opening is vertically aligned with a corresponding edge of the first opening; and

filling the second opening with the conductive material to form a second interconnect structure.

17. The method of claim 16 , further comprising:

forming a bump over the second interconnect structure, wherein a center point of the bump is vertically aligned with a center point of the second interconnect structure.

18. The method of claim 16 , wherein:

applying the grinding process to the molding compound layer until a top surface of a connector of the semiconductor structure is exposed.

19. The method of claim 18 , wherein:

the connector is in contact with the first interconnect structure.

20. The method of claim 16 , wherein:

the second interconnect structure is over the first interconnect structure.