MULTI-LEVEL SEMICONDUCTOR DEVICE AND STRUCTURE WITH MEMORY
A multilevel semiconductor device, including: a first level including a first array of first memory cells, each cell includes one first transistor; a second level including a second array of second memory cells, each cell includes one second transistor; a third level including a third array of third memory cells, each cell includes one third transistor, where second level overlays first level and third level overlays second level; memory control circuits connected so to individually control cells of the first, second and third memory cells, an array of units, each unit includes a plurality of the first, second and third memory cells and a portion of the memory control circuits, the array of units includes at least four rows and four columns of units, at least one of the first transistor is self-aligned to at least one of the third transistor, being formed following the same lithography step.
1 - 20 . (canceled)
21 . A method to process a 3D device, the method comprising:
providing a first level comprising a first single crystal silicon layer and a plurality of first transistors;
providing a second level comprising a second single crystal silicon layer;
performing an epitaxial growth of a SiGe layer on top of said second single crystal silicon layer;
performing an epitaxial growth of a third single crystal silicon layer on top of said SiGe layer;
forming a plurality of second transistors comprising said third single crystal silicon layer; and then
bonding said second level onto said first level.
22 . The method according to claim 21 , further comprising:
after said bonding step, and then, removing said second single crystal silicon layer.
23 . The method according to claim 21 , further comprising:
prior to said bonding step, etching at least a portion of said SiGe layer.
24 . The method according to claim 21 ,
wherein said first level comprises an array of memory cells.
25 . The method according to claim 21 , further comprising:
forming memory control circuits,
wherein said memory control circuits comprise said plurality of second transistors.
26 . The method according to claim 21 ,
wherein said bonding is a hybrid type bond.
27 . The method according to claim 21 , further comprising:
processing a through layer via substantially through said third single crystal silicon layer.
28 . A method to process a 3D device, the method comprising:
providing a first level comprising a first single crystal silicon layer, a plurality of first transistors, and an array of memory cells,
wherein each of said memory cells comprises at least one of said plurality of first transistors;
providing a second level comprising a second single crystal silicon layer, a plurality of second transistors, and memory control circuits,
wherein said memory control circuits comprise said second transistors; and then performing a hybrid bonding of said second level onto said first level,
wherein said hybrid bonding comprises oxide to oxide bonding and metal to metal bonding.
29 . The method according to claim 28 , further comprising:
after said bond step, removing at least a portion of said second single crystal silicon layer.
30 . The method according to claim 28 ,
wherein said second level comprises a layer of SiGe.
31 . The method according to claim 28 ,
wherein said array of memory cells is a 3D array comprising a plurality of self-aligned cells.
32 . The method according to claim 28 , further comprising:
performing an epitaxial growth of a third single crystal silicon layer over said second single crystal silicon layer.
33 . The method according to claim 28 , further comprising:
after said bonding step, performing an etching step to remove at least a portion of said second single crystal silicon layer.
34 . The method according to claim 28 , further comprising:
processing a through layer via substantially through said second single crystal silicon layer.
35 . A method to process a 3D device, the method comprising:
providing a first level comprising a first single crystal silicon layer, a plurality of first transistors, and an array of memory cells,
wherein each of said memory cells comprises at least one of said first transistors;
providing a second level comprising a second single crystal silicon layer, a plurality of second transistors, and memory control circuits,
wherein said memory control circuits comprise said second transistors; and then performing a hybrid bonding of said second level onto said first level,
wherein said hybrid bonding comprises oxide to oxide bonding and metal to metal bonding, and
wherein said second level comprises a ‘cut layer’.
36 . The method according to claim 35 , further comprising:
after said bond step, removing at least a portion of said second single crystal silicon layer, wherein said removing utilizes said ‘cut layer’.
37 . The method according to claim 35 ,
wherein said ‘cut layer’ comprises SiGe.
38 . The method according to claim 35 ,
wherein said ‘cut layer’ comprises silicon oxide.
39 . The method according to claim 35 ,
wherein said array of memory cells is a 3D array comprising a plurality of self-aligned cells.
40 . The method according to claim 35 , further comprising:
processing a through layer via substantially through said second single crystal silicon layer.