Semiconductor device and process for fabricating the same
View Patent ↗A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.
1. A stacked semiconductor device comprising:
a daughter board having an upper surface and a lower surface, the daughter board including a plurality of bump electrodes that are fixed on the lower surface; and
a first semiconductor device electrically connected with the bump electrodes and fixed on the upper surface of the daughter board,
wherein the daughter board comprises
wires in the daughter board or on the upper surface of the daughter board, and
a plurality of terminal electrodes that are electrically connected with respective ones of the wires and are exposed to the upper surface of the daughter board,
wherein the first semiconductor device comprises
a first semiconductor substrate having one surface and another surface, the first semiconductor substrate including a circuit element on the one surface,
a multilayer wiring part on the one surface of the first semiconductor substrate,
a first insulating layer that covers the multilayer wiring part,
a plurality of through-type electrodes that pierce through the first semiconductor substrate from a specified depth of the multilayer wiring part, and that contact the first semiconductor substrate through an insulating film, and
protruding electrodes, each of which are electrically connected with respective ones of the through-type electrodes, and
wherein the bump electrodes are electrically connected with the through-type electrodes through the protruding electrodes, and are larger in diameter than the protruding electrodes and the through-type electrodes.
2. The stacked semiconductor device according to claim 1 , further comprising a second semiconductor device on the first semiconductor device at an opposite side from the daughter board.
3. The stacked semiconductor device according to claim 2 , wherein the second semiconductor device includes second through-type electrodes.
4. The stacked semiconductor device according to claim 2 , further comprising a third semiconductor device at a same side of the first semiconductor device as the second semiconductor device.
5. The stacked semiconductor device according to claim 4 , further comprising a fourth semiconductor device on the second semiconductor device, the fourth semiconductor device having a same configuration as the second semiconductor device.
6. The stacked semiconductor device according to claim 5 , wherein upper surfaces of the second semiconductor device and the fourth semiconductor device are both directed toward a same direction.
7. The stacked semiconductor device according to claim 2 , wherein an insulating resin is filled between the first semiconductor device and the second semiconductor device.
8. The stacked semiconductor device according to claim 2 , wherein each of the protruding electrodes has a diameter that is larger than a diameter of each of the through-type electrodes.
9. The stacked semiconductor device according to claim 1 , wherein the first semiconductor device is a silicon semiconductor substrate.
10. The stacked semiconductor device according to claim 1 , wherein each of the protruding electrodes are electrically connected with respective ones of wires in the multilayer wiring part, and are exposed from the one surface of the first semiconductor substrate.