IP Library › Granted Patent US 10,680,639
Granted Patent B2
US 10,680,639 · App. 16/225,805 · Granted Jun 9, 2020

Circuit device, vibration device, electronic apparatus, and vehicle

Inventors: Atsushi Tanaka (Minowa, JP); Fumikazu Komatsu (Okaya, JP)
Assignee: Seiko Epson Corporation
H03M3/464H03F3/45H03F3/45475H03L1/022H03M1/804H03M3/426H03M3/474H03F2203/45156H03F2203/45512H03F2203/45551
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Quick Facts
Patent No.
US 10,680,639
App. No.
16/225,805
Granted
Jun 9, 2020
Kind
B2
Abstract

A circuit device includes an A/D converter circuit that performs A/D conversion by successive approximation using a charge redistribution type D/A converter circuit having capacitor array circuits on the positive electrode side and the negative electrode side, and quantization error hold circuits that hold charges corresponding to a quantization error in the A/D conversion. The quantization error hold circuits include quantization error hold circuits on the positive electrode side and the negative electrode side having one ends connected to sampling nodes of the capacitor array circuits on the positive electrode side and the negative electrode side. The quantization error hold circuits on the positive electrode side and the negative electrode side are placed on a second direction side orthogonal to a first direction in which the capacitor array circuits on the positive electrode side and the negative electrode side are placed.

Claims (79)

1. A circuit device comprising:

an A/D converter circuit that includes a charge redistribution type D/A converter circuit and performs A/D conversion of an input voltage by successive approximation using the D/A converter circuit; and

a quantization error hold circuit that holds a charge corresponding to a quantization error in the A/D conversion of the input voltage,

wherein the D/A converter circuit includes

a capacitor array circuit on a positive electrode side, and

a capacitor array circuit on a negative electrode side,

the A/D converter circuit includes

a comparator circuit having a first input node connected to a sampling node on the positive electrode side serving as a sampling node of the capacitor array circuit on the positive electrode side and having a second input node connected to a sampling node on the negative electrode side serving as a sampling node of the capacitor array circuit on the negative electrode side,

the quantization error hold circuit includes

a quantization error hold circuit on the positive electrode side having one end connected to the sampling node on the positive electrode side, and

a quantization error hold circuit on the negative electrode side having one end connected to the sampling node on the negative electrode side,

the capacitor array circuit on the positive electrode side and the capacitor array circuit on the negative electrode side are placed along a first direction, and

the quantization error hold circuit on the positive electrode side is placed on a second direction side of the capacitor array circuit on the positive electrode side, and the quantization error hold circuit on the negative electrode side is placed on the second direction side of the capacitor array circuit on the negative electrode side, wherein the second direction is a direction orthogonal to the first direction,

wherein the A/D converter circuit includes an adder circuit that receives an input voltage on the positive electrode side and an input voltage on the negative electrode side as the input voltage, and

the adder circuit outputs a voltage obtained by adding the input voltage on the positive electrode side and a voltage corresponding to a charge held in the quantization error hold circuit on the negative electrode side to the capacitor array circuit on the positive electrode side, and outputs a voltage obtained by adding the input voltage on the negative electrode side and a voltage corresponding to a charge held in the quantization error hold circuit on the positive electrode side to the capacitor array circuit on the negative electrode side.

2. The circuit device according to claim 1 ,

wherein the comparator circuit is placed between the capacitor array circuit on the positive electrode side and the capacitor array circuit on the negative electrode side.

3. The circuit device according to claim 1 ,

wherein the adder circuit includes an operational amplifier having an inverting input node connected to another end of the quantization error hold circuit on the positive electrode side and having a non-inverting input node connected to another end of the quantization error hold circuit on the negative electrode side, and

the operational amplifier is placed between the quantization error hold circuit on the positive electrode side and the quantization error hold circuit on the negative electrode side.

4. A circuit device, comprising:

an A/D converter circuit that includes a charge redistribution type D/A converter circuit and performs A/D conversion of an input voltage by successive approximation using the D/A converter circuit;

a quantization error hold circuit that holds a charge corresponding to a quantization error in the A/D conversion of the input voltage,

wherein the D/A converter circuit includes

a capacitor array circuit on a positive electrode side, and

a capacitor array circuit on a negative electrode side,

the A/D converter circuit includes

a comparator circuit having a first input node connected to a sampling node on the positive electrode side serving as a sampling node of the capacitor array circuit on the positive electrode side and having a second input node connected to a sampling node on the negative electrode side serving as a sampling node of the capacitor array circuit on the negative electrode side,

the quantization error hold circuit includes

a quantization error hold circuit on the positive electrode side having one end connected to the sampling node on the positive electrode side, and

a quantization error hold circuit on the negative electrode side having one end connected to the sampling node on the negative electrode side,

the capacitor array circuit on the positive electrode side and the capacitor array circuit on the negative electrode side are placed along a first direction, and

the quantization error hold circuit on the positive electrode side is placed on a second direction side of the capacitor array circuit on the positive electrode side, and the quantization error hold circuit on the negative electrode side is placed on the second direction side of the capacitor array circuit on the negative electrode side, wherein the second direction is a direction orthogonal to the first direction; and

a selector that receives first to n-th voltages to output any one of the first to n-th voltages as the input voltage, n being an integer of 2 or more,

wherein the quantization error hold circuit on the positive electrode side includes first to n-th hold circuits on the positive electrode side that hold charges corresponding to the first to n-th voltages, and

the quantization error hold circuit on the negative electrode side includes first to n-th hold circuits on the negative electrode side that hold charges corresponding to the first to n-th voltages.

5. The circuit device according to claim 4 ,

wherein the first to n-th hold circuits on the positive electrode side are placed along the second direction, and

the first to n-th hold circuits on the negative electrode side are placed along the second direction.

6. The circuit device according to claim 4 ,

wherein the A/D converter circuit uses charges held in an i-th hold circuit on the positive electrode side and an i-th hold circuit on the negative electrode side as charges corresponding to a quantization error in (k−1)th A/D conversion of an i-th voltage to perform k-th A/D conversion on the i-th voltage, and outputs A/D conversion result data in which the quantization error is noise-shaped, wherein k is an integer of 2 or more and i is an integer from 1 to n.

7. The circuit device according to claim 4 ,

wherein first to m-th temperature detection voltages from first to m-th temperature sensors are input to the selector as first to m-th voltages of the first to n-th voltages, wherein m is an integer from 1 to n.

8. A circuit device, comprising:

an A/D converter circuit that includes a charge redistribution type D/A converter circuit and performs A/D conversion of an input voltage by successive approximation using the D/A converter circuit;

a quantization error hold circuit that holds a charge corresponding to a quantization error in the A/D conversion of the input voltage,

wherein the D/A converter circuit includes

a capacitor array circuit on a positive electrode side, and

a capacitor array circuit on a negative electrode side,

the A/D converter circuit includes

a comparator circuit having a first input node connected to a sampling node on the positive electrode side serving as a sampling node of the capacitor array circuit on the positive electrode side and having a second input node connected to a sampling node on the negative electrode side serving as a sampling node of the capacitor array circuit on the negative electrode side,

the quantization error hold circuit includes

a quantization error hold circuit on the positive electrode side having one end connected to the sampling node on the positive electrode side, and

a quantization error hold circuit on the negative electrode side having one end connected to the sampling node on the negative electrode side,

the capacitor array circuit on the positive electrode side and the capacitor array circuit on the negative electrode side are placed along a first direction, and

the quantization error hold circuit on the positive electrode side is placed on a second direction side of the capacitor array circuit on the positive electrode side, and the quantization error hold circuit on the negative electrode side is placed on the second direction side of the capacitor array circuit on the negative electrode side, wherein the second direction is a direction orthogonal to the first direction;

a digital signal processing circuit that outputs frequency control data based on A/D conversion result data corresponding to the input voltage which is a temperature detection voltage; and

an oscillation signal generator circuit that generates an oscillation signal of an oscillation frequency corresponding to the frequency control data by using a vibrator.

9. A vibration device comprising:

the circuit device according to claim 1 ; and

a vibrator that is connected to the circuit device.

10. An electronic apparatus comprising:

the circuit device according to claim 1 .

11. A vehicle comprising:

the circuit device according to claim 1 .

12. A vibration device comprising:

the circuit device according to claim 4 ; and

a vibrator that is connected to the circuit device.

13. An electronic apparatus comprising:

the circuit device according to claim 4 .

14. A vehicle comprising:

the circuit device according to claim 4 .

15. A vibration device comprising:

the circuit device according to claim 8 ; and

a vibrator that is connected to the circuit device.

16. An electronic apparatus comprising:

the circuit device according to claim 8 .

17. A vehicle comprising:

the circuit device according to claim 8 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2018
From: TANAKA, ATSUSHI; KOMATSU, FUMIKAZU
To: SEIKO EPSON CORPORATION
Reel/Frame 047818/0821 →
Priority Claims (1)
JP 2017-254043 · Dec 28, 2017 · national
Continuity (1)
Related Publication 20190207621A1 · Jul 4, 2019