Power transistor leakage current with gate voltage less than threshold
An example method provides a power MOSFET, a voltage source coupled to the power MOSFET, and a current measurement device coupled to a first non-control terminal of the power MOSFET. The voltage source, the current measurement device, and a second non-control terminal of the power MOSFET couple to ground. The method uses the voltage source to apply a voltage between a gate terminal and the second non-control terminal of the power MOSFET, the voltage greater than zero volts and less than a threshold voltage of the power MOSFET. The method also uses the current measurement device to measure a first current flowing through the first non-control terminal while applying the voltage. The method further uses the first current to predict a second current through the first non-control terminal for a voltage between the gate terminal and the second non-control terminal that is approximately zero.
1. A process, comprising:
providing a power transistor having a first non-control terminal, a second non-control terminal, and a gate, a first voltage source coupled to the first non-control terminal of the power transistor, and a current measurement device coupled to the first non-control terminal of the power transistor, the first voltage source, the current measurement device, and the second non-control terminal of the power transistor being coupled to ground;
using a second voltage source to apply a gate voltage between the gate terminal and the second non-control terminal of the power transistor, the gate voltage being greater than zero volts and less than a threshold voltage of the power transistor;
using the current measurement device to measure a first current flowing through the first non-control terminal while applying the gate voltage; and
using the first current to predict a second current through the first non-control terminal for a voltage between the gate terminal and the second non-control terminal that is approximately zero.
2. The process of claim 1 , in which the power transistor is an n-type power transistor, and the first voltage between the gate terminal and the second non-control terminal is a gate terminal-to-source terminal voltage (Vgs).
3. The process of claim 1 , in which the power transistor is a p-type power transistor, and the first voltage between the gate terminal and the second non-control terminal is a source terminal-to-gate terminal voltage (Vsg).
4. The process of claim 1 , including discarding the power transistor based on the second current.
5. The process of claim 1 , in which the first non-control terminal is a drain terminal of the power transistor.
6. The process of claim 1 , in which the gate voltage is a fixed voltage.
7. The process of claim 1 , in which the second non-control terminal is a source terminal.
8. The process of claim 1 , including actuating a switch coupled to the gate terminal of the power transistor.
9. A process, comprising:
(a) providing a power transistor having a first non-control terminal, a second non-control terminal, a gate, and a threshold voltage;
(b) coupling a first voltage source to the first non-control terminal of the power transistor;
(c) coupling a current measurement device to the first non-control terminal of the power transistor;
(d) coupling the first voltage source, the current measurement device, and the second non-control terminal of the power transistor to ground;
(e) applying a gate voltage greater than zero volts and less than the threshold voltage of the power transistor between the gate terminal and the second non-control terminal of the power transistor using a second voltage source;
(f) measuring a first current flowing through the first non-control terminal while applying the gate voltage using the current measurement device; and
(g) using the first current, predicting a second current through the first non-control terminal for a voltage between the gate terminal and the second non-control terminal that is approximately zero.
10. The process of claim 9 in which the applying includes applying a fixed gate voltage.
11. The process of claim 9 in which applying includes applying multiple gate voltages in a voltage sweep.
12. The process of claim 9 in which applying includes applying multiple gate voltages in a voltage sweep until the first current reaches a threshold current level.
13. The process of claim 9 including isolating the first non-control terminal from a voltage source.
14. The process of claim 9 in which the coupling a first voltage source to the first non-control terminal of the power transistor includes coupling the first voltage source to an output node
15. The process of claim 9 in which the coupling a current measurement device to the first non-control terminal of the power transistor includes coupling the current measurement device between an output node coupled to the first non-control terminal and the first voltage source.
16. The process of claim 9 in which the predicting includes calculating leakage current when the voltage between the gate terminal and the second non-control terminal of the power transistor is zero volts.
17. The process of claim 9 in which the applying includes applying a voltage pulse.