3D memory array clusters and resulting memory architecture
A memory architecture for 3-dimensional thyristor cell arrays is disclosed. Thyristor memory cells are connected in a 3-dimensional cross-point array to form a bit line cluster. The bit line clusters are connected in parallel to sense amplifier and write circuits through multiplexer/demultiplexer circuits. Control circuits select one of the bit line clusters during a read or write operation while the non-selected bit line clusters are not activated to avoid disturbs and power consumption in the non-selected bit line clusters. The bit line clusters, multiplexer/demultiplexer circuits, and sense amplifier and write circuits from a memory array tile (MAT).
1. A memory array tile (MAT) for thyristor memory cells in an integrated circuit comprising:
a plurality of 3-dimensional thyristor memory cell arrays, each 3-dimensional array having:
a plurality of thyristor memory cells arranged in a set of parallel planes, each thyristor memory cell having first and second terminals aligned in the plane of the memory cell;
a plurality of first conducting lines, each first conducting line connected to the first terminals of the thyristor memory cells in one of the set of planes;
a plurality of second conducting lines, each second conducting line connected to a second terminal of a thyristor memory cell in each one of the planes; each of the plurality of second conducting lines has a first transistor connected to one of the third conducting lines and a second transistor connected to a voltage source for maintaining information stored in each of the plurality of thyristor memory cells;
a plurality of third conducting lines, each third conducting line controllably connected to a subset of second conducting lines;
each of the plurality of second conducting lines has a first transistor connected to one of the third conducting lines and a second transistor connected to a voltage source for maintaining information stored in each of the plurality of thyristor memory cells;
sense amplifiers and write circuits;
a multiplexer/demultiplexer connected to the first conducting lines of each of the plurality of 3-dimensional thyristor memory cell arrays, the multiplexer/demultiplexer selectively connecting the sense amplifiers and write circuits to one of the plurality of 3-dimensional thyristor memory cell arrays during read or write operations; and
control circuits selectively connecting the one of the plurality of 3-dimensional thyristor memory cell arrays to the sense amplifiers and write circuits.
2. The memory array tile of claim 1 wherein the first transistor is located at a first end and the second transistor at a second end of each of the plurality of second conducting lines.
3. The memory array tile of claim 1 wherein the second transistor comprises an MOS transistor which is weakly on to connect the voltage source to the corresponding second conducting line.
4. The memory array tile of claim 3 wherein the second transistor comprises a PMOS transistor.
5. The memory array tile of claim 1 wherein in the selective connection of the one of the plurality of 3-dimensional thyristor memory cell arrays to the sense amplifiers and write circuits, the control circuits connect one of the plurality of third conducting lines in the selectively connected one of the plurality of 3-dimensional thyristor memory cell arrays, and disconnect a remainder of the plurality of third conducting lines in the selectively connected one of 3-dimensional thyristor memory cell arrays.
6. The memory array tile of claim 5 wherein all of the plurality of second conducting lines in a 3-dimensional thyristor memory cell array not selectively connected by control circuits are connected to a voltage source to maintain thyristor memory cells connected to the plurality of second conducting lines in standby.
7. The memory array tile of claim 6 wherein each of the plurality of second conducting lines is connected to the voltage source by an MOS transistor which is weakly on.
8. The memory array tile of claim 7 wherein the MOS transistor comprises a PMOS transistor.
9. The memory array tile (MAT) of claim 1 wherein the number of first conducting lines comprises a number of bits of an Input/Output word of the memory array tile.
10. An integrated circuit having a memory comprising:
a plurality of memory array tiles (MATs), each memory array tile (MATs) further comprising:
a plurality of 3-dimensional thyristor memory cell arrays, each 3-dimensional array having:
a plurality of thyristor memory cells arranged in a set of planes parallel to a surface of a semiconductor substrate, each thyristor memory cell having first and second terminals;
a plurality of first conducting lines, each first conducting line connected to the first terminals of the thyristor memory cells in one of the set of planes;
a plurality of second (segment) conducting lines, each second conducting line connected to a second terminal of a thyristor memory cell in each one of the planes;
a plurality of third conducting lines, each third conducting line controllably connected to a subset of second conducting lines;
each of the plurality of second conducting lines has a first transistor connected to one of the third conducting lines and a second transistor connected to a voltage source for maintaining information stored in each of the plurality of thyristor memory cells;
sense amplifiers and write circuits; and
a multiplexer/demultiplexer connected to the first conducting lines of each of the plurality of 3-dimensional thyristor memory cell arrays, the multiplexer/demultiplexer selectively connecting the sense amplifiers and write circuits to one of the plurality of 3-dimensional thyristor memory cell arrays during read or write operations.
11. The memory array tile of claim 10 wherein the first transistor is located at a first end and the second transistor at a second end of each of the plurality of second conducting lines.
12. The memory array tile of claim 10 wherein the second transistor comprises an MOS transistor which is weakly on to connect the voltage source to the corresponding second conducting line.
13. The memory array tile of claim 12 wherein the second transistor comprises a PMOS transistor.
14. The integrated circuit of claim 10 wherein each memory array tile (MAT) further comprises:
control circuits selectively connecting the one of the plurality of 3-dimensional thyristor memory cell arrays to the sense amplifiers and write circuits.
15. The integrated circuit of claim 10 wherein the number of first conducting lines comprises a number of bits of an Input/Output word of the memory array tile.
16. The integrated circuit of claim 10 wherein each memory array tile (MAT) further comprises:
a second plurality of 3-dimensional thyristor memory cell arrays, each 3-dimensional array having:
a second plurality of thyristor memory cells arranged in the set of planes, each thyristor memory cell having first and second terminals;
a second plurality of first conducting lines, each first conducting line connected to the first terminals of the thyristor memory cells in one of the set of planes;
a second plurality of second conducting lines, each second conducting line connected to a second terminal of a thyristor memory cell in each one of the planes;
a second plurality of third conducting lines, each third conducting line controllably connected to a subset of second conducting lines;
each of the second plurality of second conducting lines has a first transistor connected to one of the third conducting lines of the second plurality of second conduting lines and a second transistor connected to a voltage source for maintaining information stored in each of the second plurality of thyristor memory cells; and
wherein the multiplexer/demultiplexer is connected to the first conducting lines of each of the second plurality of 3-dimensional thyristor memory cell arrays, the multiplexer/demultiplexer selectively connecting the sense amplifiers and write circuits to one of the second plurality of 3-dimensional thyristor memory cell arrays during read or write.