IP Library Granted Patent US 10,962,960
Granted Patent B2
US 10,962,960 · App. 16/227,220 · Granted Mar 30, 2021

Chip removal apparatus and information processing apparatus

Inventor: Yoshihiko Tarui (Yamanshi, JP)
Assignee: Fanuc Corporation
G05B19/418G06N20/00G05B2219/35181
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Quick Facts
Patent No.
US 10,962,960
App. No.
16/227,220
Granted
Mar 30, 2021
Kind
B2
Abstract

Provided is an information processing apparatus which determines a discharge condition for a chip removal apparatus which discharges an object in order to remove chips, wherein the information processing apparatus observes data indicating a removal efficiency of the chips as a state variable representing a current state of an environment, acquires label data indicating the discharge condition, and learns the state variable and the label data in association with each other.

Claims (23)

1. An information processing apparatus which determines a discharge condition indicating values of air or fluid discharged by a chip removal apparatus in order to remove chips, the information processing apparatus comprising:

a processor configured to:

observe data indicating a removal efficiency of the chips, obtained when performing prescribed chip removal operation under a prescribed discharge condition indicating prescribed values of the air or the fluid discharged by the chip removal apparatus, as a state variable representing a current state of an environment;

acquire determination data indicating a propriety determination result of the removal efficiency of the chips; and

learn a correlation between the adjustment of the discharge condition and the removal efficiency of the chips using the state variable and the determination data, by:

obtaining a reward related to the propriety determination result; and

updating, using the reward, a function representing a value of the discharge condition with respect to the removal efficiency of the chips,

wherein the processor learns the value of an action of adjustment of the discharge condition that is made when the removal efficiency of chips is observed so as to learn a correlation between the adjustment of the discharge condition and the removal efficiency of chips.

2. The information processing apparatus according to claim 1 , wherein the processor is further configured to output, based on a learning result, a command value based on the discharge condition.

3. The information processing apparatus according to claim 1 , wherein the information processing apparatus exists on a cloud server.

4. The information processing apparatus according to claim 1 , wherein

the processor is further configured to calculate the state variable and the determination data in a multilayered structure.

5. The information processing apparatus according to claim 1 , wherein

the processor is further configured to learn the discharge condition using the state variable and the determination data obtained for each of a plurality of the chip removal apparatuses.

6. A chip removal apparatus which discharges an object in order to remove chips, the chip removal apparatus comprising:

an information processing apparatus which determines a discharge condition indicating values of air or fluid discharged by the chip removal apparatus, wherein

the information processing apparatus includes a processor configured to:

observe data indicating a removal efficiency of the chips, obtained when performing prescribed chip removal operation under a prescribed discharge condition indicating prescribed values of the air or the fluid discharged by the chip removal apparatus, as a state variable representing a current state of an environment;

acquire determination data indicating a propriety determination result of the removal efficiency of the chips; and

learn a correlation between the adjustment of the discharge condition and the removal efficiency of the chips using the state variable and the determination data, by:

obtaining a reward related to the propriety determination results; and

updating, using the reward, a function representing a value of the discharge condition with respect to the removal efficiency of the chips, and wherein

the processor learns the value of an action of adjustment of the discharge condition that is made when the removal efficiency of chips is observed so as to learn a correlation between the adjustment of the discharge condition and the removal efficiency of chips.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2019
From: TARUI, YOSHIHIKO
To: FANUC CORPORATION
Reel/Frame 048650/0046 →
Priority Claims (1)
JP JP2017-249339 · Dec 26, 2017 · national
Continuity (1)
Related Publication 20190196454A1 · Jun 27, 2019
Cited By (1)
US 12,734,705