Lightweight checkpoint technique for resilience against soft errors
Systems and methods for implementing a lightweight checkpoint technique for resilience against soft errors are disclosed. The technique provides effective, safe, and timely soft error detection and recovery using software. In an exemplary aspect, resilience against data flow errors and control flow errors is provided in critical or mixed-critical applications in each basic block or at critical basic blocks. Verified register preservation is provided at each basic block, along with memory preservation checkpoints. In this manner, soft errors are quickly detected and addressed. The register and memory preservation further allows for safe re-execution from recoverable soft errors. Control flow errors can also be detected at the beginning and/or end of each basic block.
1. A method of detecting and recovering from soft errors of a processing device, comprising:
storing an initial state of a first register at a preservation memory address;
executing an instruction block comprising a store instruction at a target memory address;
before executing the instruction block, determining whether a control flow error occurred in a previous instruction;
if the control flow error occurred, executing a control flow diagnosis routine;
prior to executing the store instruction, preserving backup data stored in the target memory address in a memory backup register;
after preserving the backup data, storing result data from the instruction block at the target memory address;
detecting an error in the result data; and
in response to detecting the error, recovering from the error.
2. The method of claim 1 , further comprising:
identifying a set of registers used in the instruction block; and
storing an initial state of each of the set of registers at a corresponding preservation memory address of a set of preservation memory addresses.
3. The method of claim 2 , wherein recovering from the error comprises:
restoring the backup data to the target memory address; and
restoring the initial state of each of the set of registers.
4. The method of claim 3 , wherein recovering from the error further comprises re-executing the instruction block.
5. The method of claim 1 , further comprising:
determining whether the error is recoverable; and
if the error is recoverable, restoring the initial state of the first register and restoring the backup data to the target memory address.
6. The method of claim 5 , wherein determining whether the error is recoverable comprises determining the error is recoverable if the result data was stored in the target memory address.
7. The method of claim 5 , further comprising if the error is not recoverable, flagging an unrecoverable error.
8. The method of claim 1 , further comprising verifying the initial state of the first register has been accurately preserved before executing the instruction block.
9. The method of claim 1 , wherein executing the instruction block comprises performing a main instruction thread using a main set of registers and a redundant shadow instruction thread using a shadow set of registers.
10. The method of claim 9 , further comprising comparing the result data stored at the target memory address with shadow result data in a corresponding register of the shadow set of registers.
11. The method of claim 9 , further comprising verifying the initial state of the first register has been accurately preserved before executing the instruction block by:
loading from the preservation memory address into the first register; and
comparing the first register with a corresponding register of the shadow set of registers.
12. The method of claim 1 , wherein the control flow diagnosis routine comprises:
determining whether the control flow error is a wrong direction error; and
if the control flow error is the wrong direction error, restoring previously stored program counter data to a program counter register.