Amplification circuit, and receiving circuit, semiconductor apparatus and semiconductor system using the amplification circuit
An amplification circuit configured to generate an output signal by differentially amplifying first and second input signals. The first and second input signals are a differential signal pair. Alternatively, the first input signal is a single-ended signal, and the second input signal is a reference signal. The amplification circuit is configured to perform a differential amplification operation by increasing a gain for generating an output signal based on the first input signal.
1. An amplification circuit comprising:
a load circuit coupled between a high-voltage rail and first and second output nodes;
a first input circuit coupled between the first output node and a first common node, and configured to change a voltage level of the first output node based on a first input signal;
a second input circuit coupled between the second output node and a second common node, and configured to change a voltage level of the second output node based on a second input signal, and output an output signal through the second output node;
a source resistor coupled between the first and second common nodes;
a first capacitor coupled between the first common node and a low-voltage rail;
a second capacitor coupled between the second common node and the low- voltage rail; and
a gain booster configured to receive the first input signal and change a voltage level of the second common node.
2. The amplification circuit according to claim 1 , wherein the load circuit comprises:
a first load resistor coupled between the high-voltage rail and the first output node; and
a second load resistor coupled between the high-voltage rail and the second output node.
3. The amplification circuit according to claim 1 , wherein the first input circuit comprises a first transistor having a gate configured to receive the first input signal, a drain coupled to the first output node, and a source coupled to the first common node.
4. The amplification circuit according to claim 1 , wherein the second input circuit comprises a second transistor having a gate configured to receive the second input signal, a drain coupled to the second output node, and a source coupled to the second common node.
5. The amplification circuit according to claim 1 , wherein the source resistor comprises a programmable resistor having a variable resistance value.
6. The amplification circuit according to claim 1 , wherein the gain booster comprises a boosting capacitor having one terminal configured to receive the first input signal and the other terminal coupled to the second common node.
7. The amplification circuit according to claim 1 , wherein the first input signal comprises a single-ended signal, and the second input signal comprises a reference voltage having a voltage level corresponding to the middle of the range in which the first input signal swings.
8. An amplification circuit comprising:
a load circuit coupled between a high-voltage rail and first and second output nodes;
a first input circuit coupled between the first output node and a first common node, and configured to change a voltage level of the first output node based on a first input signal;
a second input circuit coupled between the second output node and a second common node, and configured to change a voltage level of the second output node based on a second input signal, and output an output signal through the second output node;
a source resistor coupled between the first and second common nodes;
a first programmable capacitor coupled between the first common node and a low-voltage rail;
a second programmable capacitor coupled between the second common node and the low-voltage rail; and
a gain booster configured to receive the first input signal and change a voltage level of the second common node.
9. The amplification circuit according to claim 8 , wherein the load circuit comprises:
a first load resistor coupled between the high-voltage rail and the first output node; and
a second load resistor coupled between the high-voltage rail and the second output node.
10. The amplification circuit according to claim 8 , wherein the first input circuit comprises a first transistor having a gate configured to receive the first input signal, a drain coupled to the first output node, and a source coupled to the first common node.
11. The amplification circuit according to claim 8 , wherein the second input circuit comprises a second transistor having a gate configured to receive the second input signal, a drain coupled to the second output node, and a source coupled to the second common node.
12. The amplification circuit according to claim 8 , wherein the source resistor comprises a programmable resistor having a variable resistance value.
13. The amplification circuit according to claim 8 , wherein the first programmable capacitor has different capacitance from the second programmable capacitor.
14. The amplification circuit according to claim 8 , wherein as the capacitance of the first programmable capacitor increases, the capacitance of the second programmable capacitor decreases.
15. The amplification circuit according to claim 8 , wherein the gain booster comprises a boosting capacitor having one terminal configured to receive the first input signal and the other terminal coupled to the second common node.
16. The amplification circuit according to claim 8 , wherein the first input signal comprises a single-ended signal, and the second input signal comprises a reference voltage having a voltage level corresponding to the middle of the range in which the first input signal swings.
17. An amplification circuit comprising:
a load circuit coupled between a high-voltage rail and first and second output nodes;
a first input circuit coupled between the first output node and a first common node, and configured to change a voltage level of the first output node based on a first input signal;
a second input circuit coupled between the second output node and a second common node, and configured to change a voltage level of the second output node based on a second input signal, and output an output signal through the second output node;
a source resistor coupled between the first and second common nodes;
a capacitor coupled between the first common node and a low-voltage rail, the capacitor comprising a programmable capacitor having variable capacitance; and
a gain booster configured to receive the first input signal and change a voltage level of the second common node.
18. The amplification circuit according to claim 17 , wherein the load circuit comprises:
a first load resistor coupled between the high-voltage rail and the first output node; and
a second load resistor coupled between the high-voltage rail and the second output node.
19. The amplification circuit according to claim 17 , wherein the first input circuit comprises a first transistor having a gate configured to receive the first input signal, a drain coupled to the first output node, and a source coupled to the first common node.
20. The amplification circuit according to claim 17 , wherein the second input circuit comprises a second transistor having a gate configured to receive the second input signal, a drain coupled to the second output node, and a source coupled to the second common node.
21. The amplification circuit according to claim 17 , wherein the source resistor comprises a programmable resistor having a variable resistance value.
22. The amplification circuit according to claim 17 , wherein the gain booster comprises a boosting capacitor having one terminal configured to receive the first input signal and the other terminal coupled to the second common node.
23. The amplification circuit according to claim 17 , wherein the first input signal comprises a single-ended signal, and the second input signal comprises a reference voltage having a voltage level corresponding to the middle of the range in which the first input signal swings.
24. An amplification circuit comprising:
a load circuit coupled between a high-voltage rail and first and second output nodes;
a first transistor having a gate configured to receive a first input signal, a drain coupled to the first output node, and a source coupled to a first common node:
a second transistor having a gate configured to receive a second input signal, a drain coupled to the second output node, and a source coupled to a second common node;
a source resistor coupled between the first and second common nodes;
a first capacitor coupled between the first common node and a low-voltage rail:
a second capacitor coupled between the second common node and the low-voltage rail; and
a gain booster configured to receive the first input signal and change a voltage level of the second common node.