Area efficient traffic generator
A packet generation and inspection system for monitoring the performance of one or more flows on a packet network comprises a processor and memory coupled to each other and to a network bus. The memory stores instructions to be executed by the processor and data to be modified by the execution of the instructions. A processor-controlled arbiter is coupled with the processor and the network bus, and upon reception of a packet on the bus or prior to transmission of a packet on the bus for one of said flows, the arbiter requests execution by the processor of selected instructions stored in the memory by providing the processor with the address of the selected instructions in the memory. The memory provides the processor with data associated with the selected instructions, and the processor modifies the data upon execution of the selected instructions.
1. A system to monitor the performance of one or more flows on a packet network, said system comprising:
a processor and memory coupled to each other and to a bus of the packet network, said memory storing commands to be executed by said processor;
an arbiter coupled with said processor and said bus, said arbiter requesting execution, upon reception or transmission of a packet on the bus, of one or more commands in said memory, and
wherein said memory provides said processor with data associated with the selected commands, and said processor modifies said data.
2. The system of claim 1 further comprising a traffic generator creating and transmitting test packets to said arbiter, and a traffic inspector receiving and analyzing said test packets to gather performance statistics and sends said statistics to said arbiter.
3. The system of claim 1 in which said processor is implemented as a field programmable gate array (FPGA).
4. A method to monitor the performance at a network device coupled to a packet network, said method comprising:
storing in association in a memory commands to be executed by a processor and data to be modified by the execution of said commands;
said memory and said processor being coupled to each other and to a bus and wherein said commands are pre-programmed in said processor,
upon reception of a packet on the bus or prior to transmission of a packet on the bus, an arbiter requesting execution by said processor of selected commands stored in said memory by providing said processor with the address of said selected commands.
5. The method of claim 4 which further includes creating and sending test packets to said bus, receiving test packets from said bus, analyzing received test packets to gather performance statistics, and sending said statistics to said processor.
6. The method of claim 4 in which processor is implemented as a field programmable gate array (FPGA).