Wafer level package structure and wafer level packaging method

1. A wafer level packaging method, comprising:

providing a device wafer having a first front surface and a first back surface opposing the first front surface, wherein at least one first chip is integrated on the first front surface of the device wafer;

forming a first oxide layer on the first front surface of the device wafer;

providing at least one second chip having a to-be-bonded surface;

forming a second oxide layer on the to-be-bonded surface of each second chip;

providing a carrier wafer;

temporally bonding a surface of the second chip opposing the second oxide layer to the carrier wafer;

forming an encapsulation layer on the carrier wafer between adjacent second chips of the at least one second chip, the encapsulation layer exposing a top of the second oxide layer; and

bonding the device wafer and the second chip by bonding the first oxide layer and the second oxide layer using a low-temperature fusion bonding process.

2. The method according to claim 1 , wherein the low-temperature fusion bonding process comprises:

sequentially performing a plasma activation process, a deionized water cleaning process and a drying process on a surface of the first oxide layer and a surface of the second oxide layer;

after the drying process, correspondingly aligning and attaching the first oxide layer with the second oxide layer, according to a preset relative position relationship between the first chip and the second chip, and applying a pressure to the device wafer and the second chip to perform a pre-bonding treatment; and

after the pre-bonding treatment, performing an annealing treatment on the device wafer and the second chip.

3. The method according to claim 1 , after forming the encapsulation layer and before performing the low-temperature fusion bonding process, further comprising:

forming a third oxide layer on the encapsulation layer,

wherein:

a top of the third oxide layer levels with a top of the second oxide layer; and

the third oxide layer and the second oxide layer are made of a same material.

4. The method according to claim 1 , after forming the encapsulation layer and before the low-temperature fusion bonding process, further comprising:

de-bonding the second chip from the carrier wafer.

5. The method according to claim 2 , after the pre-bonding treatment and before the annealing treatment, further comprising:

de-bonding the second chip from the carrier wafer.

6. The method according to claim 1 , after the low-temperature fusion process, further comprising:

de-bonding the second chip from the carrier wafer.

7. The method according to claim 1 , after the low-temperature fusion bonding process, further comprising:

thinning the first back surface of the device wafer.

8. The method according to claim 1 , wherein:

the first oxide layer is made of one of silicon oxide, hafnium oxide, aluminum oxide, and lanthanum oxide;

the second oxide layer is made of one of silicon oxide, hafnium oxide, aluminum oxide, and lanthanum oxide; and

the first oxide layer and the second oxide layer are made of a same material.

9. The method according to claim 2 , wherein:

a reaction gas of the plasma activation process includes at least one of Ar, N 2 , O 2 , and SF 6 .

10. The method according to claim 2 , wherein:

a radio frequency power of the plasma activation process is in a range of approximately 20 W-200 W;

a process pressure of the plasma activation process is in a range of approximately 0.1 mbar-10 mbar; and

a process time of the plasma activation process is in a range of approximately 0.1 minute-10 minutes.

11. The method according to claim 2 , wherein:

a bonding pressure of the pre-bonding treatment process is in a range of approximately 1 Newton-20 Newton; and

a process time of the pre-bonding treatment process is in a range approximately 1 second-60 seconds.

12. The method according to claim 2 , wherein:

a process temperature of the annealing treatment is in a range of approximately 200° C.-500° C.; and

a process time of the annealing treatment is in a range of approximately 20 minutes-200 minutes.

13. The method according to claim 1 , wherein:

any of the first oxide layer and the second oxide layer are formed by one of an atomic layer deposition process, a low-pressure chemical vapor deposition process, a metal-organic chemical vapor deposition process, a physical vapor deposition process and a pulsed laser deposition process.

14. The method according to claim 1 , wherein:

the second chip has a second front surface formed with at a least one soldering pad and a second back surface opposing the second front surface; and

one of the second front surface and the second back surface is used for the bonding.

15. A wafer level package structure, comprising:

a device wafer having a first front surface and a first back surface opposing the front surface, wherein at least one first chip is integrated in the first front surface and a first oxide layer is formed on the first front surface;

a second chip bonded with the device wafer, wherein the second chip has a to-be-bonded surface, a second oxide layer is formed on the to-be-bonded surface, and the second oxide layer and the first oxide layer are bonded together, wherein orthographic projections of the first and second chips on a plane of an interface between the first and second oxide layers are non-overlapped; and

an encapsulation layer formed on the first oxide layer, the encapsulation layer exposing a surface of the second chip opposing the to-be-bonded surface.

16. The wafer level package structure according to claim 15 , further comprising:

a third oxide layer formed between the encapsulation layer and the first oxide layer and made of a material the same as a material of the first oxide layer.

17. The wafer level package structure according to claim 15 , wherein:

a thickness of the first oxide layer is in a range of approximately 1000 Å-30000 Å; and

a thickness of the second oxide layer is in a range of approximately 1000 Å-30000 Å.

18. The wafer level package structure according to claim 15 , wherein:

the first oxide layer is made of one of silicon oxide, hafnium oxide, aluminum oxide and lanthanum oxide;

the second oxide layer is made of one of silicon oxide, hafnium oxide, aluminum oxide and lanthanum oxide; and

the first oxide layer and the second oxide layer are made of a same material.

19. The wafer level package structure according to claim 15 , wherein:

the second chip comprises:

a second front surface that is formed with at least one soldering pad; and

a second back surface opposing the second front surface,

wherein the to-be-bonded surface is one of the second front surface containing the at least one soldering pad and the second back surface.

20. The wafer level package structure according to claim 15 , further comprising:

at least a first via structure formed in the device wafer and electrically connected to the first chip; and

at least a second via structure formed in the device wafer and electrically connected to the second chip.