Array substrate
View Patent ↗The array substrate taught by the present invention have dummy ITO lines on the fanout lines configured as multiple segments separated at intervals so that, when two neighboring dummy ITO lines are short-circuited, the place of short circuit is limited to a segment of the neighboring dummy ITO lines. Coupling capacitance is limited to that between the segments and fanout lines. Compared to prior arts where coupling capacitance occurs between neighboring dummy ITO lines and fanout lines, the present invention has much smaller coupling capacitance, thereby reducing the impact of coupling capacitance to signal transmission on the fanout lines, avoiding the occurrence of light lines on the display panel, and enhancing the display effect of the display panel.
1. An array substrate, comprising a display area,
a non-display area surrounding the display area,
a plurality of signal lines within the display area,
control chips within the non-display area,
a plurality of fanout lines separated at intervals within the non-display area,
a plurality dummy indium tin oxide (ITO) lines separated at intervals within the non-display area, and
a first insulation layer,
wherein the signal lines comprise scan lines and data lines stacked above the scan lines;
the plurality of the fanout lines are electrically connected between one control chip and the scan lines for transmitting scan signals to the scan lines;
another plurality of fanout lines are electrically connected between another control chip and the data lines for transmitting data signals to the data lines;
the dummy ITO lines are stacked above the fanout lines;
the dummy ITO lines and the fanout lines are separated by the first insulation layer;
each dummy ITO line comprises a plurality of ITO segments separated at intervals along an extension direction of the corresponding fanout line,
the fanout lines connecting the scan lines and the fanout lines connecting the data lines comprise first fanout lines and second fanout lines;
the first fanout lines and the scan lines are formed in a same process in a first layer;
the second fanout lines and the data lines are formed in a same process in a second layer;
each of the first and second fanout lines corresponds to a dummy ITO line;
the first fanout lines and the second fanout lines have alternate and non-overlapping vertical projections; and
each dummy ITO line and its corresponding fanout line have partially overlapped vertical projections.
2. The array substrate according to claim 1 , further comprising a second insulation layer, wherein each fanout line comprises a first conductive line and a second conductive line stacked above the first conductive line; and the first and second conductive lines are separated by the second insulation layer.
3. The array substrate according to claim 2 , wherein the second insulation layer has a plurality of vias arranged at intervals; and the first conductive lines and second conductive lines are electrically connected together through the vias.
4. The array substrate according to claim 2 , wherein the first and second conductive lines have an identical resistance.
5. The array substrate according to claim 3 , wherein the first and second conductive lines have an identical resistance.
6. The array substrate according to claim 4 , wherein the first and second conductive lines are made of a same conductive material;
and the first and second conductive lines are of a same line width.
7. The array substrate according to claim 5 , wherein the first and second conductive lines are made of a same conductive material;
and the first and second conductive lines are of a same line width.
8. The array substrate according to claim 2 , wherein the first conductive lines' projections onto the second conductive lines are overlapped with the second conductive lines.
9. The array substrate according to claim 1 , wherein the control chips comprise a scan driving chip and a data driving chip.