IP Library Granted Patent US 10,971,494
Granted Patent B2
US 10,971,494 · App. 16/231,067 · Granted Apr 6, 2021

Semiconductor device and semiconductor integrated circuit

Inventor: Masanori Yoshitani (Yokohama, JP)
Assignee: SOCIONEXT, INC.
H01L27/0924H01L29/0642H01L29/0847H01L29/41758H01L29/4238H01L29/42356H01L29/78H01L29/785H01L29/7851H01L21/823437
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Quick Facts
Patent No.
US 10,971,494
App. No.
16/231,067
Granted
Apr 6, 2021
Kind
B2
Abstract

A semiconductor device includes: element isolation regions; a projecting semiconductor region; a plurality of first gate electrodes each formed on both side surfaces and a top surface of a portion of the projecting semiconductor region, the plurality of first gate electrodes being formed between a pair of opposed end portions of the element isolation regions and being component elements of a plurality of transistors; at least one second gate electrode formed between the first gate electrodes, in the same layer as a layer where the plurality of first gate electrodes are formed, and applied with a voltage for turning off the transistor.

Claims (12)

1. A semiconductor device comprising:

element isolation insulating regions formed in a substrate and including first and second opposed end portions which are opposed to each other;

a projecting semiconductor region formed on the substrate and extending from the first opposed end portion to the second opposed end portion;

a pair of dummy gate electrodes formed adjacent to the first and second opposed end portions and formed on both side surfaces and a top surface of both end portions of the projecting semiconductor region, the dummy gate electrodes being electrically floating;

a plurality of first gate electrodes each formed on both side surfaces and a top surface of a first portion of the projecting semiconductor region, the plurality of first gate electrodes being formed between the pair of dummy gate electrodes and being component elements of a plurality of first transistors which are configured to be driven according to signals input to the first gate electrodes, each of the plurality of first transistors being a FinFET; and

at least one second gate electrode formed on both side surfaces and a top surface of a second portion of the projecting semiconductor region, the second portion being different from the first portions, the second gate electrode being formed between the first gate electrodes and between the pair of dummy gate electrodes in parallel with the first gate electrodes, in the same layer as a layer where the plurality of first gate electrodes are formed, and being a component element of a second transistor which is applied with a gate voltage such that the second transistor is turned off.

2. The semiconductor device according to claim 1 , wherein the second gate electrode is applied as the gate voltage with a voltage equal to a voltage of a back gate of the second transistor.

3. The semiconductor device according to claim 1 , wherein the second gate electrodes are formed between respective ones of the plurality of first gate electrodes, respectively.

4. The semiconductor device according to claim 1 , wherein the second gate electrodes are formed between respective sets of the first gate electrodes, respectively, the sets each consisting of adjacent two of the first gate electrodes.

5. The semiconductor device according to claim 1 , further comprising:

source regions and drain regions formed in the projecting semiconductor region at both sides of the first gate electrodes and the second gate electrode, and

wherein the plurality of first transistors and the plurality of second transistors include the source regions and drain regions.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 8, 2019
From: YOSHITANI, MASANORI
To: SOCIONEXT INC.
Reel/Frame 048550/0863 →
Continuity (2)
Continuation PCTJP2016069089 · Jun 28, 2016
Related Publication 20190131303A1 · May 2, 2019