IP Library › Granted Patent US 10,763,016
Granted Patent B2
US 10,763,016 · App. 16/231,937 · Granted Sep 1, 2020

Method of manufacturing a chip component

Inventors: Hiroshi Tamagawa (Kyoto, JP); Hiroki Yamamoto (Kyoto, JP); Katsuya Matsuura (Kyoto, JP); Yasuhiro Kondo (Kyoto, JP)
Assignee: ROHM CO., LTD.
H01C1/14H01C10/16H01C10/50H01C17/006H01C17/23H01F27/2804H01F27/40H01F29/00H01F29/08H01F41/041H01G2/16H01G4/33H01G4/38H01G4/40H01G5/011H01G5/38H01G5/40H01L24/32H01L25/105H01L25/13H01L27/0802H01L27/15H01L33/62H05K1/181H05K3/3442H05K3/3478H01F17/0006H01L2221/68304H01L2224/16225H01L2924/12041H01L2924/12042H01L2924/15788H01L2924/181H01L2924/351H01L2933/0066H05K2201/1003H05K2201/10015H05K2201/10022H05K2201/10106H05K2201/10212H05K2203/0415Y02P70/613
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Quick Facts
Patent No.
US 10,763,016
App. No.
16/231,937
Granted
Sep 1, 2020
Kind
B2
Abstract

A method for manufacturing a chip component includes forming an element, which includes a plurality of element parts, on a substrate. A plurality of fuses are formed, for disconnectably connecting each of the plurality of element parts to an external connection electrode. The external connection electrode, which is arranged to provide external connection for the element, is formed by electroless plating on the substrate.

Claims (15)

1. A method for manufacturing a chip component, comprising:

forming an element, which includes a plurality of element parts, on a substrate;

forming a plurality of fuses for disconnectably connecting each of the plurality of element parts to an external connection electrode; and

forming the external connection electrode, which is arranged to provide external connection for the element, by electroless plating on the substrate,

wherein the element parts are resistor bodies, and the chip component is a chip resistor,

wherein the resistor bodies are formed by:

forming a resistor body film on a top surface of the substrate;

forming a wiring film in contact with the resistor body film; and

forming the plurality of resistor bodies by patterning the resistor body film and the wiring film, and

wherein the fuses are formed in the patterning of the resistor body film and the wiring film.

2. The method for manufacturing a chip component according to claim 1 , wherein the external connection electrode includes a Ni layer and an Au layer, and the Au layer is exposed at a topmost surface.

3. The method for manufacturing a chip component according to claim 2 , wherein the external connection electrode further includes a Pd layer interposed between the Ni layer and the Au layer.

4. The method for manufacturing a chip component according to claim 1 , wherein the wiring film includes a pad on which the external connection electrode is to be formed, and the external connection electrode is formed on the pad.

5. The method for manufacturing a chip component according to claim 4 , further comprising forming, on the substrate, a protective film that covers the element and exposes the pad,

wherein the external connection electrode is formed on the pad exposed from the protective film.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 24, 2018
From: TAMAGAWA, HIROSHI; YAMAMOTO, HIROKI; MATSUURA, KATSUYA; KONDO, YASUHIRO
To: ROHM CO., LTD.
Reel/Frame 047849/0790 →
Priority Claims (9)
JP 2012-015573 · Jan 27, 2012 · national
JP 2012-015574 · Jan 27, 2012 · national
JP 2012-039181 · Feb 24, 2012 · national
JP 2012-039182 · Feb 24, 2012 · national
JP 2012-042301 · Feb 28, 2012 · national
JP 2012-060556 · Mar 16, 2012 · national
JP 2012-081628 · Mar 30, 2012 · national
JP 2012-085668 · Apr 4, 2012 · national
JP 2012-272742 · Dec 13, 2012 · national
Continuity (3)
Continuation 15490333 · Apr 18, 2017
Continuation 14373900
Related Publication 20190148040A1 · May 16, 2019
Cited By (2)
US 12,316,035 US 12,690,199