Semiconductor device having a multilayer wiring structure
A semiconductor device having a plurality of first wirings (X-direction) which include a first power supply line and a second power supply line, a plurality of third wirings (X-direction) which include a third (fourth) power supply line that is located above the first (second) power supply line and is electrically connected to the first (second) power supply line. The semiconductor device also has a plurality of second wirings (Y-direction) that include a first (second) connection wiring located above the first (second) power supply line and below the third (fourth) power supply line that is electrically connected to the first (second) power supply line and to the third (fourth) power supply line.
1. A semiconductor device comprising:
a first standard cell;
a plurality of first wirings extending in a first direction in a plan view;
a plurality of second wirings formed above the first wirings and extending in a second direction different from the first direction in a plan view; and
a plurality of third wirings formed above the second wirings and extending in the first direction in a plan view, wherein:
the plurality of first wirings include a first power supply line and a second power supply line;
the plurality of third wirings include a third power supply line that is located above the first power supply line and electrically connected to the first power supply line,
the plurality of third wirings include a fourth power supply line that is located above the second power supply line and electrically connected to the second power supply line;
the plurality of second wirings include a first connection wiring that is located above the first power supply line and below the third power supply line and electrically connected to the first power supply line and to the third power supply line and extends in the second direction in a plan view;
the plurality of second wirings include a second connection wiring that is located above the second power supply line and below the fourth power supply line and electrically connected to the second power supply line and to the fourth power supply line and extends in the second direction in a plan view,
the first standard cell includes the first power supply line, the second power supply line, the third power supply line, the fourth power supply line, the first connection wiring and the second connection wiring,
the third power supply line is superposed on the first power supply line in a plan view; and
the fourth power supply line is superposed on the second power supply line in a plan view.
2. The semiconductor device according to claim 1 , wherein
the plurality of second wirings include a first signal line that is located between the first connection wiring and the second connection wiring in a plan view and extends in the second direction in a plan view, and
the standard cell includes the first signal line.
3. The semiconductor device according to claim 2 , wherein
the plurality of third wirings include a second signal line that is electrically connected to the first signal line, and
the first standard cell includes the second signal line.
4. The semiconductor device according to claim 3 , further comprising a second standard cell arranged side by side with the first standard cell in a plan view,
wherein the second standard cell includes a first output wiring, and
the second signal line is electrically connected to the first output wiring of the second standard cell.
5. The semiconductor device according to claim 3 , wherein
the plurality of first wirings include a third signal line that is electrically connected to the first signal line, and
the first standard cell includes the third signal line.
6. The semiconductor device according to claim 3 , wherein
the third power supply line is wider than the second signal line, and
the fourth power supply line is wider than the second signal line.
7. The semiconductor device according to claim 2 , further comprising
a first NMOS transistor that includes a first source, a first drain and a first gate, and
a first PMOS transistor that includes a second source, a second drain and a second gate,
wherein
the first NMOS transistor is located between the first power supply line and the first PMOS transistor in the second direction in a plan view,
the first PMOS transistor is located between the second power supply line and the first NMOS transistor in the second direction in a plan view,
the first source is electrically connected to the first power supply line,
the second source is electrically connected to the second power supply line, and
the first standard cell includes the first NMOS transistor and the first PMOS transistor.
8. The semiconductor device according to claim 7 , wherein
the plurality of the second wirings include a fourth signal line that extends to the second direction in a plan view,
the first gate is connected to the second gate,
the first gate and the second gate are electrically connected to the first signal wiring,
the first drain and the second drain are electrically connected to the second signal wiring.
9. The semiconductor device according to claim 8 , wherein
a first space is located between the first connection wiring and the first signal line in a plan view,
a second space is located between the second connection wiring and the first signal line in a plan view, and
the fourth signal line is located adjacent to the first signal wiring in the second direction in a plan view.
10. The semiconductor device according to claim 9 , wherein
the first space is located adjacent to the fourth signal line in the first direction in a plan view, and
the second space is located adjacent to the fourth signal line in the first direction in a plan view.
11. The semiconductor device according to claim 8 , wherein
a first part of the fourth signal line is superposed on the first power supply line in a plan view, and
a second part of the fourth signal line is superposed on the second power supply line in a plan view.
12. The semiconductor device according to claim 8 , wherein
a first part of the fourth signal line is located under the third power supply line in a plan view, and
a second part of the fourth signal line is located under the fourth power supply line in a plan view.
13. The semiconductor device according to claim 8 , further comprising a third standard cell that is located adjacent to the first standard cell in the second direction in a plan view,
wherein
the fourth signal line is connected to a wiring of the third standard cell.
14. The semiconductor device according to claim 7 , wherein
the first NMOS transistor includes a first fin,
the first PMOS transistor includes a second fin,
the first source and the first drain are formed in the first fin, and
the second source and the second drain are formed in the second fin.
15. The semiconductor device according to claim 7 , wherein
the first NMOS transistor includes a first nanowire,
the first PMOS transistor includes a second nanowire,
the first nanowire is located between the first source and the first drain,
the second nanowire is located between the second source and the second drain,
the first gate is located on the first nanowire, and
the second gate is located on the second nanowire.
16. The semiconductor device according to claim 2 , further comprising
a first NMOS transistor that includes a first source, a first drain and a first gate,
a first PMOS transistor that includes a second source, a second drain and a second gate,
a second NMOS transistor that includes a third source, a third drain and a third gate,
a second PMOS transistor that includes a fourth source, a fourth drain and a fourth gate
wherein
the first NMOS transistor is located between the first power supply line and the first PMOS transistor in the second direction in a plan view,
the first PMOS transistor is located between the second power supply line and the first NMOS transistor in the second direction in a plan view,
the second NMOS transistor is located between the first power supply line and the second PMOS transistor in the second direction in a plan view,
the second PMOS transistor is located between the second power supply line and the second NMOS transistor in the second direction in a plan view,
the first source is electrically connected to the first power supply line,
the second source is electrically connected to the second power supply line,
the fourth source is electrically connected to the second power supply line,
the third source is electrically connected to the first drain,
the third drain is electrically connected to the second drain and the fourth drain,
the first gate is electrically connected to the second gate,
the third gate is electrically connected to the fourth gate,
the first signal line is electrically connected to the first gate and the second gate, and
the first standard cell includes the first NMOS transistor, the first PMOS transistor, the second NMOS transistor and the second PMOS transistor.
17. The semiconductor device according to claim 16 , wherein
the plurality of second wirings include a third connection wiring that is located above the first power supply line and below the third power supply line and electrically connected to the first power supply line and to the third power supply line and extends in the second direction in a plan view;
the plurality of second wirings include a fourth connection wiring that is located above the second power supply line and below the fourth power supply line and electrically connected to the second power supply line and to the fourth power supply line and extends in the second direction in a plan view,
the plurality of second wirings include a second signal line that is located between the third connection wiring and the fourth connection wiring in a plan view and extends in the second direction in a plan view,
the first connection wiring and the third connection wiring are arranged in the first direction in a plan view,
the second connection wiring and the fourth connection wiring are arranged in the first direction in a plan view,
the second signal line is electrically connected to the third gate and the fourth gate, and
the first standard cell includes the third connection wiring, the fourth connection wiring and the second signal line.
18. The semiconductor device according to claim 1 , wherein
the third power supply line is wider than the first power supply line, and
the fourth power supply line is wider than the second power supply line.
19. The semiconductor device according to claim 1 , wherein
the plurality of first wirings is formed by damascene method,
the plurality of second wirings is formed by damascene method, and
the plurality of third wirings is formed by damascene method.
20. The semiconductor device according to claim 1 , wherein
the first power supply line includes Cu,
the first power supply line includes a first barrier layer that includes Ta,
the second power supply line includes Cu,
the second power supply line includes a second barrier layer that includes Ta,
the third power supply line includes Cu,
the third power supply line includes a third barrier layer that includes Ta,
the fourth power supply line includes Cu,
the fourth power supply line includes a fourth barrier layer that includes Ta,
the first connection wiring includes Cu,
the first connection wiring includes a fifth barrier layer that includes Ta,
the second connection wiring includes Cu, and
the second connection wiring includes a sixth barrier layer that includes Ta.