Methods and apparatus for a dynamic addressing decimation filter

1. An apparatus for incremental analog-digital conversion, comprising:

an analog modulator comprising:

a multi-level quantizer, configured to control a total number of toggling quantizer levels; and

a multi-bit dynamically addressing decimation filter, comprising:

a controller;

a set of physical sub decimation filters, where a total number of physical sub decimation filters is less than the total number of toggling quantizer levels; and

a post processing circuit.

2. The apparatus of claim 1 , wherein the analog modulator further comprises:

an analog input coupled from an external device; and

an output coupled to an input of the controller and the set of physical sub decimation filters.

3. The apparatus of claim 1 , wherein the controller is further configured to:

receive a coded value output from the multi-level quantizer at a controller input;

generate a position encoded value;

output a position encoded value to a select input of the set of physical sub decimation filters;

manage a plurality of virtual sub decimation filters; and

check for errors.

4. The apparatus of claim 1 , wherein each physical sub decimation filter is further configured to:

receive a coded value output from the multi-level quantizer at a first sub decimation filter input;

receive a position encoded value output from the controller at a second sub decimation filter input; and

route the coded value output from the multi-level quantizer to the post processing circuit.

5. The apparatus of claim 1 , wherein the post processing circuit is further configured to:

receive data from the set of physical sub decimation filters;

correct, sum, or scale the data from at least one of the set of physical sub decimation filters and a plurality of virtual sub decimation filters; and

generate a digital output according to the received data.

6. The apparatus of claim 1 , wherein each physical sub decimation filter further comprises a multiplexer and a digital filter.

7. The apparatus of claim 1 , wherein the post processing circuit further comprises a weighted coefficient generator.

8. The apparatus of claim 1 , wherein an output terminal of the multi-level quantizer is connected to a first input terminal of each physical sub decimation filter from the set of physical sub decimation filters.

9. The apparatus of claim 1 , wherein an output terminal of the controller is connected to:

a second input terminal of each physical sub decimation filter from the set of physical sub decimation filters; and

an input terminal of the post processing circuit.

10. The apparatus of claim 1 , wherein the post processing circuit is connected to an output terminal of each physical sub decimation filter from the set of physical sub decimation filters.

11. A method for incremental analog-digital conversion, comprising:

analog modulating comprising controlling a number of toggling quantizer levels; and

dynamically addressing a multi-bit decimation filter, comprising:

receiving a quantizer coded value;

generating a position encoded value according to the received quantizer coded value;

addressing a set of physical sub decimation filters according to the generated position encoded value;

routing the quantizer coded value according to the addressed set of physical sub decimation filters;

managing a number of virtual sub decimation filters according to the quantizer coded value;

filtering the quantizer coded value; and

generating a digital output according to the filtered quantizer coded value.

12. The method of claim 11 , wherein dynamically addressing the multi-bit decimation filter further comprises checking for errors.

13. The method of claim 11 , wherein dynamically addressing the multi-bit decimation filter further comprises performing at least one of: correcting, summing, and scaling values received from the set of physical sub decimation filters and a controller.

14. The method of claim 11 , wherein dynamically addressing the multi-bit decimation filter further comprises generating a weighted coefficient.

15. The method of claim 14 , wherein dynamically addressing the multi-bit decimation filter further comprises performing at least one of: correcting, summing, and scaling values received from the set of physical sub decimation filters with the weighted coefficient.

16. A system, comprising:

a sensor; and

an incremental analog-to-digital converter (ADC) connected to the sensor and configured to:

receive an analog input signal from the sensor; and

generate a digital output signal according to the analog input signal, comprising:

converting the analog input signal to a quantizer value from a total number of quantizer values;

generating a position encoded value based on the quantizer value; and

addressing a plurality of sub decimation filters using the position encoded value, wherein a number of the plurality of sub decimation filters is less than the total number of quantizer values.

17. The system of claim 16 , wherein the ADC comprises:

a multi-level quantizer configured to convert the analog input signal to the quantizer value; and

a multi-bit dynamically addressing decimation filter, comprising:

a controller responsive to the multi-level quantizer; and

the plurality of sub decimation filters; wherein each sub decimation filter is responsive to the controller and the multi-level quantizer.

18. The system of claim 17 , wherein each sub decimation filter from the plurality of sub decimation filters comprises a multiplexer and a digital filter.

19. The system of claim 17 , wherein the controller is further configured to:

receive the quantizer value from the multi-level quantizer;

generate the position encoded value; and

transmit the position encoded value to the plurality of sub decimation filters.

20. The system of claim 16 , wherein the ADC is further configured to apply a weighted coefficient to the digital output signal.