Methods and apparatus for an amplifier circuit

1. An operational amplifier, comprising:

a first cross-connect circuit responsive to a first clock signal having a first phase and a third clock signal having a third phase and configured to receive a first input signal and a second input signal;

an input stage circuit connected to the first cross-connect circuit and configured to apply a first gain to the first and second input signals;

a second cross-connect circuit connected to the input stage circuit and responsive to a second clock signal having a second phase and a fourth clock signal having a fourth phase;

a voltage adjustment circuit connected to the input stage circuit and configured to provide a stable voltage to the input stage circuit; and

an output stage circuit connected to the second cross-connect circuit and configured to apply a second gain to the first and second input signals and generate an output voltage;

wherein the first, second, third, and fourth clock signals are distinct from each other.

2. The operational amplifier according to claim 1 , wherein:

each of the first, second, third, and fourth phases are offset from each other; and

the first, second, third, and fourth clock signals have a same frequency.

3. The operational amplifier according to claim 2 , wherein the offset provides a period of time when the first, second, third, and fourth clock signals have a same signal level.

4. The operational amplifier according to claim 1 , wherein the first cross-connect circuit comprises:

a first switch responsive to the first clock signal;

a second switch in parallel with the first switch and responsive to the third clock signal;

a third switch in series with the first switch and responsive to the third clock signal; and

a fourth switch in series with the second switch and responsive to the first clock signal.

5. The operational amplifier according to claim 4 , wherein:

the input stage circuit comprises a differential transistor pair comprising NMOS transistors; and

the first, second, third, fourth switches comprise PMOS transistors.

6. The operational amplifier according to claim 4 , wherein:

the first cross-connect circuit comprises a third node located between the first and third switches and a fourth node located between the second and fourth switches; and

the input stage circuit comprises a differential transistor pair comprising a first transistor and a second transistor, wherein the first transistor is connected to the third node and the second transistor is connected to the fourth node.

7. The operational amplifier according to claim 4 , where the second cross-connect circuit comprises:

a fifth switch responsive to the second clock signal;

a sixth switch in parallel with the fifth switch and responsive to the fourth clock signal;

a seventh switch in series with the fifth switch and responsive to the fourth clock signal; and

an eighth switch in series with the sixth switch and responsive to the second clock signal.

8. The operational amplifier according to claim 7 , wherein:

the input stage circuit comprises a differential transistor pair comprising PMOS transistors; and

the first, second, third, fourth switches comprise NMOS transistors.

9. A method for removing an offset voltage from an output signal of an operational amplifier, comprising:

generating:

a first clock signal having a first phase;

a second clock signal having a second phase;

a third clock signal having a third phase; and

a fourth clock signal having a fourth phase, according to a reference clock signal;

selectively transmitting a first input signal and a second input signal to an input stage circuit with a first cross-connect circuit, wherein the first cross-connect circuit comprises:

a first switch responsive to the first clock signal;

a second switch in parallel with the first switch and responsive to the third clock signal;

a third switch in series with the first switch and responsive to the third clock signal; and

a fourth switch in series with the second switch and responsive to the first clock signal;

selectively transmitting the first input signal and the second input signal from the input stage circuit to an output stage circuit with a second cross-connect circuit, wherein the second cross-connect circuit comprises:

a fifth switch responsive to the second clock signal;

a sixth switch in parallel with the fifth switch and responsive to the fourth clock signal;

a seventh switch in series with the fifth switch and responsive to the fourth clock signal; and

an eighth switch in series with the sixth switch and responsive to the second clock signal; and

regulating a voltage of the input stage circuit with a voltage adjustment circuit.

10. The method according to claim 9 , further comprising applying a first bias voltage and a second bias voltage to the input stage circuit.

11. The method according to claim 9 , wherein regulating the voltage of the input stage circuit comprises applying a third bias voltage to the voltage adjustment circuit.

12. The method according to claim 9 , wherein:

each of the first, second, third, and fourth phases are offset from each other; and

the first, second, third, and fourth clock signals have a same frequency.

13. The method according to claim 12 , wherein the offset provides a period of time when the first, second, third, and fourth clock signals have a same signal level.

14. A system, comprising:

a clock generator configured to generate: a first clock signal having a first phase, a second clock signal having a second phase, a third clock signal having a third phase, and a fourth clock signal having a fourth phase, according to a reference clock signal; wherein the first, second, third, and fourth clock signals are distinct from each other;

an operational amplifier in communication with the clock generator and comprising:

a first cross-connect circuit responsive to the first clock signal and the third clock signal and configured to receive a first input signal and a second input signal;

an input stage circuit connected to the first cross-connect circuit and configured to apply a first gain to the first and second input signals;

a second cross-connect circuit connected to the input stage circuit and responsive to the second clock signal and the fourth clock signal;

an output stage circuit connected to the second cross-connect circuit and configured to apply a second gain to the first and second input signals and generate an output voltage; and

an analog-to-digital converter (ADC) configured to:

operate according to an ADC clock; and

convert the output voltage to a digital signal.

15. The system according to claim 14 , wherein the reference clock signal is proportional to the ADC clock by a factor of 1/N, where N is a natural number.

16. The system according to claim 14 , wherein the operational amplifier further comprises a voltage adjustment circuit connected to the input stage circuit and configured to provide a stable voltage to the input stage circuit.

17. The system according to claim 14 , wherein:

each of the first, second, third, and fourth phases are offset from each other; and

the first, second, third, and fourth clock signals have a same frequency.

18. The system according to claim 14 , wherein:

the first cross-connect circuit comprises:

a first switch responsive to the first clock signal;

a second switch in parallel with the first switch and responsive to the third clock signal;

a third switch in series with the first switch and responsive to the third clock signal; and

a fourth switch in series with the second switch and responsive to the first clock signal; and

the second cross-connect circuit comprises:

a fifth switch responsive to the second clock signal;

a sixth switch in parallel with the fifth switch and responsive to the fourth clock signal;

a seventh switch in series with the fifth switch and responsive to the fourth clock signal; and

an eighth switch in series with the sixth switch and responsive to the second clock signal.

19. The system according to claim 18 , wherein:

the first cross-connect circuit further comprises a third node located between the first and third switches and a fourth node located between the second and fourth switches; and

the input stage circuit comprises a differential transistor pair comprising:

a first transistor comprising a gate terminal connected to the third node; and

a second transistor comprising a gate terminal connected to the fourth node.

20. The system according to claim 14 , wherein:

the input stage circuit is configured to operate according to a first bias voltage and a second bias voltage; and

the voltage adjustment circuit is configured to operate according to a third bias voltage.