Semiconductor apparatus
A semiconductor apparatus includes a semiconductor substrate provided with a plurality of diode ranges and a plurality of IGBT ranges. The IGBT ranges and the diode ranges are alternately arranged along a first direction in plan view of the semiconductor substrate along a thickness direction of the semiconductor substrate. Each diode range is provided with a plurality of n-type cathode regions and a plurality of p-type current-limiting regions in a range of being in contact with a lower electrode. The cathode regions and the current-limiting regions are alternately arranged along a second direction intersecting the first direction in each diode range. Each IGBT range is provided with a p-type collector region in a range of being in contact with the lower electrode. The collector region in each IGBT range is in contact with each cathode region in the adjacent diode range.
1. A semiconductor apparatus, comprising:
a semiconductor substrate;
an upper electrode disposed on an upper surface of the semiconductor substrate;
a lower electrode disposed on a lower surface of the semiconductor substrate;
a trench;
a gate insulating film; and
a gate electrode, wherein:
the semiconductor substrate is provided with a plurality of diode ranges and a plurality of IGBT ranges;
the IGBT ranges and the diode ranges are alternately arranged along a first direction in plan view of the semiconductor substrate along a thickness direction of the semiconductor substrate;
each diode range is provided with a plurality of n-type cathode regions and a plurality of p-type current-limiting regions in a range of being in contact with the lower electrode;
the n-type cathode regions and the p-type current-limiting regions are alternately arranged along a second direction intersecting the first direction in each diode range in plan view of the semiconductor substrate along the thickness direction;
each IGBT range is provided with a p-type collector region in a range of being in contact with the lower electrode;
the p-type collector region in each IGBT range is in contact with each n-type cathode region in the adjacent diode range;
the semiconductor substrate includes
an n-type drift region that is distributed over the diode ranges and the IGBT ranges, and is disposed above the n-type cathode regions, the p-type current-limiting regions, and the p-type collector regions,
a p-type body region that is distributed over the diode ranges and the IGBT ranges, is disposed above the n-type drift region, and is in contact with the upper electrode in each diode range and each IGBT range, and
an n-type emitter region that is disposed in each IGBT range, is in contact with the upper electrode, and is separated from the n-type drift region by the p-type body region;
the trench extends to have a depth passing through the n-type emitter region and the p-type body region from the upper surface of the semiconductor substrate and reaching the n-type drift region;
the gate insulating film covers an inner surface of the trench;
the gate electrode is disposed in the trench and is insulated from the semiconductor substrate by the gate insulating film;
the diode range includes a p-type hole blocking region that is in contact with at least a part of an upper surface of each n-type cathode region; and
the n-type drift region is in contact with an upper surface of the p-type hole blocking region.
2. The semiconductor apparatus according to claim 1 , wherein each n-type cathode region extends long along the first direction in plan view of the semiconductor substrate along the thickness direction.
3. The semiconductor apparatus according to claim 2 , wherein a length of each n-type cathode region in the first direction is longer than a thickness of the semiconductor substrate.
4. The semiconductor apparatus according to claim 1 , wherein:
the p-type hole blocking region is in contact with a part of an upper surface of each n-type cathode region; and
the n-type drift region is in contact with an upper surface of the n-type cathode region in a range in which the p-type hole blocking region is not present.
5. The semiconductor apparatus according to claim 4 , wherein the p-type hole blocking region is in contact with an upper surface of an end portion of the n-type cathode region in the first direction.
6. The semiconductor apparatus according to claim 1 , wherein the p-type hole blocking region is in contact with at least one of the p-type current-limiting regions.
7. The semiconductor apparatus according to claim 6 , wherein the p-type hole blocking region extends long in the second direction and is in contact with upper surfaces of the plurality of n-type cathode regions.
8. The semiconductor apparatus according to claim 7 , wherein each diode range is provided with a plurality of p-type hole blocking regions.
9. The semiconductor apparatus according to claim 1 , wherein:
the n-type drift region includes
a buffer region that is in contact with the upper surface of the n-type cathode region and has an n-type impurity concentration lower than the n-type cathode region, and
a low concentration region that is in contact with an upper surface of the buffer region and has an n-type impurity concentration lower than the buffer region; and
a p-type impurity concentration of the p-type hole blocking region is lower than a p-type impurity concentration of the p-type collector region, a p-type impurity concentration of the p-type current-limiting region, and the n-type impurity concentration of the buffer region.
10. The semiconductor apparatus according to claim 1 , wherein the trench extends long along the second direction in plan view of the semiconductor substrate along the thickness direction.