IP Library Granted Patent US 10,651,290
Granted Patent B2
US 10,651,290 · App. 16/239,470 · Granted May 12, 2020

Semiconductor device and method for fabricating the same

Inventors: Te-Chang Hsu (Tainan, TW); Chun-Chia Chen (Tainan, TW); Yao-Jhan Wang (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/66545H01L21/02326H01L21/02337H01L21/02348H01L21/3115H01L21/31053H01L21/76826H01L21/76828H01L21/76834H01L29/6656H01L29/66575H01L29/66795H01L21/76825H01L29/41791H01L29/4966H01L29/517H01L29/785
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Quick Facts
Patent No.
US 10,651,290
App. No.
16/239,470
Granted
May 12, 2020
Kind
B2
Abstract

A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a contact etch stop layer (CESL) on the gate structure, forming an interlayer dielectric (ILD) layer around the gate structure, performing a curing process so that an oxygen concentration of the CESL is different from the oxygen concentration of the ILD layer, and then performing a replacement metal gate process (RMG) process to transform the gate structure into a metal gate.

Claims (19)

1. A method for fabricating semiconductor device, comprising:

forming a gate structure on a substrate;

forming a contact etch stop layer (CESL) on the gate structure;

forming an interlayer dielectric (ILD) layer around the gate structure;

performing a curing process while the CESL is on the gate structure; and

performing a replacement metal gate process (RMG) process to transform the gate structure into a metal gate.

2. The method of claim 1 , further comprising:

forming the ILD layer on the CESL;

performing the curing process so that an oxygen concentration in the CESL and an oxygen concentration in the ILD layer are different.

3. The method of claim 2 , wherein the oxygen concentration in the ILD layer is greater than the oxygen concentration in the CESL.

4. The method of claim 2 , wherein the oxygen concentration on a surface of the CESL is greater than the oxygen concentration in the CESL.

5. The method of claim 1 , further comprising performing the curing process so that the CESL and the ILD layer comprise same dielectric constant.

6. The method of claim 1 , further comprising forming a spacer around the gate structure, wherein the spacer comprises an offset spacer and a main spacer.

7. The method of claim 6 , further comprising performing the curing process so that the main spacer, the CESL, and the ILD layer comprise same dielectric constant.

8. The method of claim 1 , further comprising:

performing a planarizing process to remove part of the ILD layer; and

performing the RMG process.

9. The method of claim 1 , wherein a temperature of the curing process is between 500° C. to 800° C.

10. The method of claim 1 , wherein a duration of the curing process is between 50 minutes to 70 minutes.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →