Semiconductor modification process for conductive and modified electrical regions and related structures
There is herein described a process for providing improved device performance and fabrication techniques for semiconductors. More particularly, the present invention relates to a process for forming features, such as pixels, on GaN semiconductors using a p-GaN modification and annealing process. The process also relates to a plasma and thermal anneal process which results in a p-GaN modified layer where the annealing simultaneously enables the formation of conductive p-GaN and modified p-GaN regions that behave in an n-like manner and block vertical current flow. The process also extends to Resonant-Cavity Light Emitting Diodes (RCLEDs), pixels with a variety of sizes and electrically insulating planar layer for electrical tracks and bond pads.
1. A method for fabricating an electronic component, comprising:
depositing a spreading layer on a p-type GaN layer of the electrical component;
depositing a mask feature onto the spreading layer over a portion of the p-type GaN layer, the mask feature exposing a portion of the spreading layer over another portion of the p-type GaN layer;
removing the portion of the spreading layer over the other portion of the p-type GaN layer;
subsequent to removing the portion of the spreading layer, exposing the other portion of the p-type GaN layer to a plasma treatment to convert the other portion of the p-type GaN layer to n-type GaN, the portion of the p-type GaN layer being shielded from the plasma treatment; and
subsequent to the plasma treatment, annealing the p-type GaN layer to form a region that blocks current flow from the n-type GaN and a conductive contact from the portion of the p-type GaN layer shielded from the plasma treatment.
2. The method of claim 1 , further comprising, prior to annealing the p-type GaN layer, removing the mask feature from the spreading layer.
3. The method of claim 1 , wherein the region that blocks current flow is non-conductive to vertical currents.
4. The method of claim 1 , wherein exposing the other portion of the p-type GaN layer to the plasma treatment includes exposing the other portion of the p-type GaN layer to a plasma for 3000 seconds with a plasma power of 200 Watts and a gas flow of 20 sccm.
5. The method of claim 1 , wherein annealing the p-type GaN layer includes one of:
exposing the p-type GaN layer to a temperature of 500° C.; or
rapid thermal annealing the p-type GaN layer for 120 seconds to a temperature of 500° C.
6. The method of claim 1 , wherein exposing the other portion of the p-type GaN layer to the plasma treatment includes exposing the other portion of the p-type GaN layer to a plasma including at least one of:
CH 3 ;
Ar;
CHF 3 /Ar;
C 2 F 6 ;
CF 4 ; or
H 2 .
7. The method of claim 1 , further comprising forming a mirror over the conductive contact and at least a portion of the region that blocks current flow.
8. The method of claim 1 , further comprising forming a mesa in the p-type GaN layer, the region that blocks current flow and the conductive contact being at a top side of the mesa opposite a base of the mesa.
9. The method of claim 8 , wherein the mesa includes a straight, sloped, or parabolic sidewall defined between the top side and the base of the mesa.
10. The method of claim 8 , wherein the base of the mesa is larger than an area of the conductive contact.
11. The method of claim 1 , further comprising forming a p-contact and an n-contact that are electrically isolated from each other by the region that blocks current flow.
12. The method of claim 1 , wherein the electrical component includes one of:
a micro light emitting diode (LED);
a resonant-cavity LED; or
a vertical cavity surface emitting layer (VCSEL).
13. A method for fabricating an electronic component, comprising:
depositing a mask feature onto a portion of a p-type GaN layer of the electrical component;
exposing another portion of the p-type GaN layer to a plasma treatment to convert the other portion of the p-type GaN layer to n-type GaN, the portion of the p-type GaN layer being shielded from the plasma treatment by the mask feature;
subsequent to the plasma treatment, removing the mask feature from the portion of the p-type GaN layer;
subsequent to the plasma treatment and removing the mask feature, depositing a spreading layer on the other portion of the p-type GaN layer; and
subsequent to the depositing the spreading layer, annealing the p-type GaN layer to form a region that blocks current flow from the n-type GaN and a conductive contact from the portion of the p-type GaN layer shielded from the plasma treatment.
14. A method for fabricating an electronic component, comprising:
depositing a spreading layer on a p-type GaN layer of the electrical component;
depositing a mask feature onto the spreading layer over a portion of the p-type GaN layer, the mask feature exposing a portion of the spreading layer over another portion of the p-type GaN layer;
exposing the portion of the spreading layer over the other portion of the p-type GaN layer and the other portion of the p-type GaN layer to a plasma treatment to convert the other portion of the p-type GaN layer to n-type GaN, the portion of the p-type GaN layer being shielded from the plasma treatment; and
subsequent to the plasma treatment, annealing the p-type GaN layer to form a region that blocks current flow from the n-type GaN and a conductive contact from the portion of the p-type GaN layer shielded from the plasma treatment.
15. The method of claim 14 , further comprising, prior to annealing the p-type GaN layer, removing the mask feature from the spreading layer.
16. The method of claim 14 , wherein the spreading layer is less than or equal to 5 um in thickness.
17. The method of claim 14 , wherein the spreading layer includes at least one of:
Ni/Au;
Ni/Pt;
Au/Pt;
Pt/Ni/Au;
Ni/Ag;
Pd; or
Ni/ITO.
18. The method of claim 14 , wherein the region that blocks current flow permits no or little lateral current conduction across the portion of the spreading layer.