IP Library Granted Patent US 11,120,941
Granted Patent B2
US 11,120,941 · App. 16/242,247 · Granted Sep 14, 2021

Methods of forming capacitors

Inventors: Jeffrey Peter Gambino (Gresham, OR); Bruce Greenwood (Gresham, OR); Angel Rodriguez (San Jose, CA)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01G4/008H01G4/10H01L27/14634H01L28/91H01L27/14609H01L28/60
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Quick Facts
Patent No.
US 11,120,941
App. No.
16/242,247
Granted
Sep 14, 2021
Kind
B2
Abstract

Implementations of methods of forming capacitors may include depositing a first metal layer over a substrate, forming a photoresist layer over the first metal layer, patterning the photoresist layer, patterning the first metal layer using the pattern of the photoresist layer, depositing a dielectric layer over the first metal layer, and depositing a second metal layer over the dielectric layer to form a metal-insulator-metal capacitor.

Claims (41)

1. A method of forming a capacitor comprising:

depositing a first metal layer over a substrate;

coupling a diblock copolymer over the first metal layer;

selectively removing a portion of the diblock copolymer;

patterning the first metal layer using a remaining portion of the diblock copolymer;

depositing a dielectric layer over the first metal layer;

depositing a second metal layer over the dielectric layer to form a metal-insulator-metal (MIM) device; and

coupling a third metal layer between the first metal layer and the dielectric layer, the third metal layer at least partially comprising a lower electrode;

wherein the first metal layer is coupled with the dielectric layer only indirectly through one or more other elements.

2. The method of claim 1 , wherein the first metal layer at least partially comprises the lower electrode.

3. The method of claim 1 , wherein the second metal layer is an upper electrode.

4. The method of claim 1 , wherein the first metal layer is a seed layer.

5. The method of claim 1 , wherein the first metal layer and the second metal layer comprise titanium.

6. A method of forming a capacitor comprising:

coupling a tungsten layer between a first metal layer and a substrate

coupling a diblock copolymer over the first metal layer;

selectively removing a portion of the diblock copolymer;

patterning the first metal layer using a remaining portion of the diblock copolymer;

depositing a dielectric layer over the first metal layer; and

depositing a second metal layer over the dielectric layer to form a metal-insulator-metal (MIM) device.

7. The method of claim 6 , further comprising coupling a third metal layer between the first metal layer and the dielectric layer, the third metal layer at least partially comprising a lower electrode.

8. The method of claim 7 , wherein the third metal layer fully physically isolates the first metal layer from the dielectric layer.

9. The method of claim 8 , wherein the first metal layer is coupled with the dielectric layer only indirectly through one or more other elements.

10. The method of claim 6 , wherein the first metal layer at least partially comprises a lower electrode.

11. The method of claim 6 , wherein the second metal layer at least partially comprises an upper electrode.

12. The method of claim 6 , wherein the first metal layer is a seed layer.

13. The method of claim 6 , wherein the first metal layer and the second metal layer comprise titanium.

14. A method of forming a capacitor comprising:

depositing a first metal layer over a substrate;

coupling a diblock copolymer over the first metal layer;

selectively removing a portion of the diblock copolymer;

patterning the first metal layer using a remaining portion of the diblock copolymer;

depositing a dielectric layer over the first metal layer; and

depositing a second metal layer over the dielectric layer to form a metal-insulator-metal (MIM) device;

wherein a capacitance of the capacitor is greater than or equal to 25 femtofarads/square micron.

15. The method of claim 14 , further comprising coupling a third metal layer between the first metal layer and the dielectric layer, the third metal layer at least partially comprising a lower electrode.

16. The method of claim 15 , wherein the first metal layer is coupled with the dielectric layer only indirectly through one or more other elements.

17. The method of claim 14 , wherein the first metal layer at least partially comprises a lower electrode.

18. The method of claim 14 , wherein the second metal layer at least partially comprises an upper electrode.

19. The method of claim 14 , wherein the first metal layer is a seed layer.

20. The method of claim 14 , wherein the first metal layer and the second metal layer comprise titanium.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 049473, FRAME 0932 Recorded Aug 17, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064618/0721 →
SECURITY INTEREST Recorded Jun 14, 2019
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 049473/0932 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 8, 2019
From: GAMBINO, JEFFREY PETER; GREENWOOD, BRUCE; RODRIGUEZ, ANGEL
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 047929/0431 →