Vertical-type memory device

1. A vertical-type memory device comprising:

a substrate including a cell array region and a connection region adjacent to the cell array region;

a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and having a stepped shape in the connection region sequentially descending toward the connection region from the cell array region;

a plurality of channel structures in the cell array region, the plurality of channel structures passing through the plurality of gate electrode layers, wherein each of the plurality of channel structures includes a first epitaxial layer in contact with the substrate, and a first channel layer on and contacting the first epitaxial layer;

a plurality of dummy channel structures in the connection region, the plurality of dummy channel structures passing through at least one of the plurality of gate electrode layers,

wherein each of the plurality of dummy channel structures includes a second epitaxial layer in contact with the substrate, and a second channel layer on and contacting the second epitaxial layer;

a first interlayer insulating layer; and

a second interlayer insulating layer,

wherein an upper surface of the substrate has a first upper surface in the cell array region and a second upper surface disposed at a higher level than the first upper surface of the substrate in the connection region,

at least one of the plurality of gate electrodes has a same level in the cell array region as in the connection region,

the plurality of gate electrode layers includes a first gate electrode layer adjacent to the substrate and a second gate electrode layer adjacent to the first gate electrode layer,

the first interlayer insulating layer is between the first gate electrode layer and the substrate,

the second interlayer insulating layer is between the first gate electrode layer and the second gate electrode layer,

an upper surface of each of the first and the second epitaxial layers is at a lower level than a lower surface in the cell array region of the second gate electrode layer,

a distance between an upper end of the first channel layer and a lower end of the first channel layer is greater than a distance between an upper end of the first epitaxial layer and a lower end of the first epitaxial layer, and

a distance between an upper end of the second channel layer and a lower end of the second channel layer is greater than a distance between an upper end of the second epitaxial layer and a lower end of the second epitaxial layer.

2. The vertical-type memory device of claim 1 ,

wherein a thickness of the second interlayer insulating layer in the cell array region is greater than a thickness of the second interlayer insulating layer in the connection region.

3. The vertical-type memory device of claim 1 ,

wherein a thickness of the first interlayer insulating layer in the cell array region is greater than a thickness of the first interlayer insulating layer in the connection region.

4. The vertical-type memory device of claim 1 , wherein

the first gate electrode layer comprises a bent portion bent along the upper surface of the substrate; and

a first interval between the lower surface of the second gate electrode layer in the cell array region and an upper surface of the first gate electrode layer in the cell array region is greater than a second interval between the lower surface of the second gate electrode layer in the connection region and the upper surface of the first gate electrode layer in the connection region.

5. The vertical-type memory device of claim 1 , further comprising contact plugs,

wherein the first gate electrode layer comprises a pad region in the connection region,

wherein the contact plugs comprise a contact plug on the pad region of the first gate electrode layer,

wherein the second gate electrode layer comprises a first portion in the cell array region and a second portion in the connection region, and

wherein the pad region of the first gate electrode layer is at a lower level than the first portion of the second gate electrode layer.

6. The vertical-type memory device of claim 1 , wherein

the second gate electrode includes an end portion in the connection region, and the end portion of the second gate electrode layer in the connection region is at a same level as a portion of the second gate electrode in the cell array region.

7. The vertical-type memory device of claim 1 , wherein

a vertical length of the plurality of channel structures is greater than a vertical length of the plurality of dummy channel structures.