Analog-to-digital drive circuitry having built-in time gain compensation functionality for ultrasound applications
A time gain compensation (TGC) circuit for an ultrasound device includes a first amplifier having an integrating capacitor and a control circuit configured to generate a TGC control signal that controls an integration time of the integrating capacitor, thereby controlling a gain of the first amplifier. The integration time is an amount of time an input signal is coupled to the first amplifier before the input signal is isolated from the first amplifier.
1. A method of controlling gain in a time gain compensation (TGC) circuit for an ultrasound device, the method comprising:
generating, by a control circuit, a TCG control signal to control an integration time of a first integrating capacitor of a first amplifier of the TGC circuit, the integration time comprising an amount of time an input signal is coupled to the first amplifier before the input signal is isolated from the first amplifier.
2. The method of claim 1 , wherein the first amplifier comprises a differential amplifier.
3. The method of claim 2 , wherein the differential amplifier comprises an analog-to-digital converter (ADC) driver.
4. The method of claim 1 , further comprising generating the TGC control signal by comparing an output voltage of a second amplifier and a threshold voltage determined by a value of a variable gain control input signal, the second amplifier configured as a comparator circuit and having a feedback capacitor.
5. The method of claim 4 , wherein the second amplifier comprises an operational amplifier.
6. The method of claim 1 , wherein the integration time controlled by the TGC control signal is dependent upon an RC time constant of the control circuit and a voltage of the variable gain control input signal.
7. The method of claim 6 , wherein an output gain of the first amplifier is proportional to a ratio between resistance and capacitance values of the control circuit and resistance and capacitance values of the first amplifier.
8. The method of claim 7 , wherein the ratio is about 5.
9. The method of claim 1 , wherein the first integrating capacitor also comprises a sample and hold capacitor of an analog-to-digital converter (ADC).
10. The method of claim 9 , further comprising storing and cancelling an offset voltage associated with the input signal to the first amplifier, and storing and cancelling an offset voltage associated with the first amplifier itself.
11. A method of driving an analog-to-digital converter (ADC) circuit, the method comprising:
generating a time gain compensation (TGC) control signal that controls an integration time of first and second integrating capacitors of a first amplifier of an analog-to-digital converter (ADC) driver circuit for an ultrasound device; and
providing, with a control circuit, time gain compensation by controlling a gain of the first amplifier by generating the time gain compensation (TGC) control signal, wherein the integration time comprises an amount of time that an input signal is coupled to the first amplifier before the input signal is isolated from the first amplifier.
12. The method of claim 11 , wherein the first amplifier comprises a differential amplifier.
13. The method of claim 12 , further comprising selectively coupling a pair of ADC sample and hold capacitors to output terminals of the differential amplifier.
14. The method of claim 13 , further comprising coupling a pair of offset voltage capacitors to input terminals of the differential amplifier.
15. The method of claim 14 , further comprising:
discharging, with a first pair of switches, the first and second integrating capacitors during a reset mode of operation;
coupling, with a second pair of switches, the input signal to the differential amplifier following the reset mode of operation, and to thereafter isolating the input signal from the differential amplifier according to the TGC control signal;
coupling, with the second pair of switches, the input signal to the offset voltage capacitors during an offset cancellation mode of operation;
equalizing, with a third pair of switches, the input and output terminals of the differential amplifier during the offset cancellation mode; and
coupling, with a fourth pair of switches, the output terminals of the differential amplifier to the ADC sample and hold capacitors during a sample mode of operation.
16. The method of claim 11 , further comprising generating the TGC control signal by comparing an output voltage of a second amplifier of the control circuit and a threshold voltage determined by a value of a variable gain control input signal, the second amplifier configured as a comparator circuit.
17. The method of claim 16 , wherein the second amplifier comprises an operational amplifier.
18. The method of claim 17 , wherein the integration time controlled by the TGC control signal is dependent upon an RC time constant and a voltage of the variable gain control input signal.
19. The method of claim 18 , further comprising charging a feedback capacitor of the control circuit is charged with a constant current such that a state of the TGC control signal changes once the output voltage of the operational amplifier exceeds the threshold voltage determined by the variable gain control input signal.
20. The method of claim 19 , further comprising selectively discharging the feedback capacitor.
21. A method of operating an ultrasound system, the method comprising:
receiving electrical signals from an ultrasonic transducer;
coupling the electrical signals to an input of an analog circuit block; and
coupling an output of the analog circuit block to an analog-to-digital converter (ADC), the analog circuit block further comprising:
an ADC driver circuit including a differential amplifier having first and second integrating capacitors configured in a feedback configuration; and a control circuit configured to provide time gain compensation by generating a time gain compensation (TGC) control signal that controls an integration time of the first and second integrating capacitors, the integration time comprising an amount of time that an input signal is coupled to the differential amplifier before the input signal is isolated from the differential amplifier.
22. The method of claim 21 , further comprising:
selectively coupling a pair of ADC sample and hold capacitors to output terminals of the differential amplifier, the differential amplifier having a pair of offset voltage capacitors coupled to input terminals of the differential amplifier;
discharging, with a first pair of switches, the first and second integrating capacitors during a reset mode of operation;
coupling, with a second pair of switches, the input signal to the differential amplifier following the reset mode of operation, and thereafter isolating the input signal from the differential amplifier according to the TGC control signal, and coupling the input signal to the offset voltage capacitors during an offset cancellation mode of operation;
equalizing, with a third pair of switches, the input and output terminals of the differential amplifier during the offset cancellation mode; and
coupling, with a fourth pair of switches, the output terminals of the differential amplifier to the ADC sample and hold capacitors during a sample mode of operation.
23. The method of claim 22 , further comprising generating the TGC control signal by comparing an output voltage of an operational amplifier of the control circuit with a threshold voltage determined by a value of a variable gain control input signal, the operational amplifier having a feedback capacitor.
24. The method of claim 23 , wherein the integration time controlled by the TGC control signal is dependent upon a capacitance of the feedback capacitor and a voltage of the variable gain control input signal.
25. The method of claim 24 , further comprising charging the feedback capacitor of the control circuit with a constant current such that a state of the TGC control signal changes once the output voltage of the operational amplifier exceeds the threshold voltage determined by the variable gain control input signal.
26. The method of claim 25 , further comprising selectively discharging the feedback capacitor with a switch of the control circuit.
27. The method of claim 21 , wherein the first and second integrating capacitors also serve as a pair of ADC sample and hold capacitors.
28. The method of claim 27 , further comprising:
discharging, with a first pair of switches, the first and second integrating capacitors during a reset mode of operation;
coupling, with a second pair of switches, the input signal to the differential amplifier following the reset mode of operation, and thereafter isolating the input signal from the differential amplifier according to the TGC control signal; and
coupling, with a third pair of switches, a common mode voltage to input and output terminals of the differential amplifier during the reset mode.
29. The method of claim 27 , further comprising:
discharging, with a first pair of switches, the first integrating capacitor during a reset mode of operation;
discharging, with a second pair of switches, a second integrating capacitor during the reset mode of operation;
equalizing, with a third pair of switches, the input and output terminals of the differential amplifier during the reset mode of operation; and
coupling, with a fourth pair of switches, the first integrating capacitor to the input and output terminals of the differential amplifier following the reset mode of operation.
30. The method of claim 27 , further comprising:
generating the TGC control signal by comparing an output voltage of an operational amplifier and a threshold voltage determined by a value of a variable gain control input signal, the operational amplifier having a feedback capacitor;
wherein the integration time controlled by the TGC control signal is dependent upon an RC time constant of the control circuit and a voltage of the variable gain control input signal.