Low voltage drive circuit with bus isolation and methods for use therewith

1. A low voltage drive circuit (LVDC) comprises:

a transmit digital to analog circuit configured to convert transmit digital data into analog outbound data;

a receive analog to digital circuit configured to convert analog inbound data into received digital data; and

a drive sense circuit configured to:

convert the analog outbound data into an analog transmit signal;

drive the analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus at a first frequency;

receive an analog receive signal from the bus; and

isolate the analog receive signal from the analog transmit signal to recover the analog inbound data, wherein the analog inbound data is represented within the analog receive signal as variances in loading of the bus at a second frequency;

wherein the drive sense circuit comprises:

a change detection circuit configured to generate the analog inbound data in response to the analog receive signal and the analog outbound data;

a regulation circuit configured to generate a regulation signal in response to the analog inbound data; and

a power source circuit configured to generate the analog transmit signal in response to the regulation signal.

2. The LVDC of claim 1 further comprises:

a controller configured to set transmit parameters of the transmit digital to analog circuit, wherein the transmit digital to analog circuit converts the transmit digital data into the analog outbound data in accordance with the transmit parameters.

3. The LVDC of claim 2 , wherein the controller is further configured to set receive parameters of the receive analog to digital circuit, wherein the receive analog to digital circuit converts the analog inbound data into the received digital data in accordance with the receive parameters.

4. The LVDC of claim 1 further comprises:

a clock circuit configured to generate a receive clock signal and a transmit clock signal, wherein the transmit analog to digital circuit converts the transmit digital data into the analog outbound data in accordance with the transmit clock signal and wherein the receive analog to digital circuit converts the analog inbound data into the received digital data in accordance with the receive clock signal.

5. The LVDC of claim 4 further comprises:

a controller configured to generate a clock control signal;

wherein the clock circuit generates the receive clock signal and the transmit clock signal in accordance with the clock control signal.

6. The LVDC of claim 1 , wherein the change detection circuit includes an operational amplifier or a comparator.

7. The LVDC of claim 1 , wherein the power source circuit includes a regulated current source configured to generate the analog transmit signal in response to the regulation signal.

8. The LVDC of claim 1 , wherein the change detection circuit is further configured to generate the analog inbound data in response to an analog reference signal.

9. The LVDC of claim 8 , wherein the change detection circuit includes an operational amplifier or a comparator.

10. A method comprises:

converting, via a transmit digital to analog circuit, transmit digital data into analog outbound data;

converting, via an receive analog to digital circuit, analog inbound data into received digital data; and

converting, via a drive sense circuit, the analog outbound data into an analog transmit signal;

driving, via the drive sense circuit, the analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus at a first frequency;

receiving, via the drive sense circuit, an analog receive signal from the bus; and

isolating, via the drive sense circuit, the analog receive signal from the analog transmit signal to recover the analog inbound data, wherein the analog inbound data is represented within the analog receive signal as variances in loading of the bus at a second frequency;

wherein the drive sense circuit comprises:

a change detection circuit configured to generate the analog inbound data in response to the analog receive signal and the analog outbound data;

a regulation circuit configured to generate a regulation signal in response to the analog inbound data; and

a power source circuit configured to generate the analog transmit signal in response to the regulation signal.

11. The method of claim 10 further comprises:

setting transmit parameters of the transmit digital to analog circuit, wherein the transmit digital to analog circuit converts the transmit digital data into the analog outbound data in accordance with the transmit parameters.

12. The method of claim 10 further comprises:

setting receive parameters of the receive analog to digital circuit, wherein the receive analog to digital circuit converts the analog inbound data into the received digital data in accordance with the receive parameters.

13. The method of claim 10 further comprises:

generating, via a clock circuit, a receive clock signal and a transmit clock signal, wherein the transmit analog to digital circuit converts the transmit digital data into the analog outbound data in accordance with the transmit clock signal and wherein the receive analog to digital circuit converts the analog inbound data into the received digital data in accordance with the receive clock signal.

14. The method of claim 13 further comprises:

generating a clock control signal;

wherein the clock circuit generates the receive clock signal and the transmit clock signal in accordance with the clock control signal.

15. The method of claim 10 , wherein the change detection circuit includes an operational amplifier or a comparator.

16. The method of claim 10 , wherein the power source circuit includes a regulated current source configured to generate the analog transmit signal in response to the regulation signal.

17. The method of claim 10 , wherein the change detection circuit is further configured to generate the analog inbound data in response to an analog reference signal.

18. The method of claim 17 , wherein the change detection circuit includes an operational amplifier or a comparator.