3D 1T1C stacked DRAM structure and method to fabricate
Embodiments disclosed herein include three-dimensional 3D arrays of memory cells and methods of forming such devices. In an embodiment a memory device comprises, a substrate surface, and a three-dimensional (3D) array of memory cells over the substrate surface. In an embodiment each memory cell comprises a transistor and a capacitor. In an embodiment the transistor of each memory cell comprises, a semiconductor channel, with a first end of the semiconductor channel electrically coupled to a bit line that runs substantially parallel to the substrate surface, and a second end of the semiconductor channel is electrically coupled to the capacitor. The transistor may also comprise a gate dielectric on a surface of the semiconductor channel between the first end and the second end of the semiconductor channel. In an embodiment, the gate dielectric is contacted by a word line that runs substantially perpendicular to the substrate surface.
1. A memory device, comprising:
a substrate surface; and
a three-dimensional (3D) array of memory cells over the substrate surface, wherein each memory cell comprises a transistor and a capacitor, the transistor comprising a semiconductor channel laterally adjacent to the capacitor in a plane parallel with the substrate surface, wherein a bit line runs substantially parallel to the substrate surface and couples memory cells along a length of the bit line and across a width of the bit line, and wherein the transistor of each memory cell comprises:
the semiconductor channel, wherein a first end of the semiconductor channel is electrically coupled to the bit line, wherein the bit line is in the plane parallel with the surface substrate, and a second end of the semiconductor channel is electrically coupled to the capacitor; and
a gate dielectric on a surface of the semiconductor channel between the first end and the second end of the semiconductor channel, wherein the gate dielectric is contacted by a word line that runs substantially perpendicular to the substrate surface.
2. The memory device of claim 1 , further comprising:
a plurality of bit lines in a stack, wherein the bit lines are separated by insulating layers.
3. The memory device of claim 2 , wherein the plurality of bit lines comprises eight or more bit lines.
4. The memory device of claim 2 , wherein each bit line is electrically coupled to two or more semiconductor channels.
5. The memory device of claim 2 , further comprising:
a spacer along sidewall surfaces of the plurality of bit lines.
6. The memory device of claim 2 , wherein the plurality of bit lines terminate in a stair step pattern.
7. The memory device of claim 1 , wherein the semiconductor channels are thin-film semiconductor channels.
8. The memory device of claim 1 , wherein each capacitor comprises:
a capacitor electrode electrically coupled to the second end of the semiconductor channel;
a capacitor dielectric over the capacitor electrode; and
a drain electrode.
9. The memory device of claim 8 , wherein the capacitor electrode and the drain electrode have interdigitated surfaces.
10. The memory device of claim 8 , wherein a plurality of capacitors share the same drain electrode.
11. The memory device of claim 10 , wherein the drain electrode extends in a direction parallel to the word line.
12. The memory device of claim 8 , wherein the capacitor electrodes have a thickness that is equal to a thickness of the bit line.
13. An electronic system, comprising:
a motherboard;
a die coupled to the motherboard, wherein the die comprises:
a substrate surface; and
a three-dimensional (3D) array of memory cells over the substrate surface, wherein each memory cell comprises a transistor and a capacitor, wherein the transistor comprises a semiconductor channel laterally adjacent to the capacitor in a plane that is substantially parallel to the substrate surface, wherein a bit line runs substantially parallel to the substrate surface and couples memory cells along a length of the bit line and across a width of the bit line, and wherein the transistor of each memory cell comprises:
the semiconductor channel, wherein a first end of the semiconductor channel is electrically coupled to the bit line, wherein the bit line is in the plane parallel with the surface substrate, and a second end of the semiconductor channel is electrically coupled to the capacitor; and
a gate dielectric on a surface of the semiconductor channel between the first end and the second end of the semiconductor channel, wherein the gate dielectric is contacted by a word line that runs substantially perpendicular to the substrate; and
wherein the capacitor of each memory cell comprises:
a capacitor electrode electrically coupled to the second end of the semiconductor channel;
a capacitor dielectric over the capacitor electrode; and
a drain electrode.
14. The electronic system of claim 13 , wherein the 3D array of memory cells is positioned in a back end metal layer of the die.