Semiconductor structure
View Patent ↗Semiconductor structures are provided. A memory cell includes a latch circuit formed by two cross-coupled inverters and a pass-gate transistor coupling an output of the latch circuit to a bit line. Each cross-coupled inverter is connected to a VDD line of a first metallization layer. A word line of a second metallization layer is connected to a gate of the pass-gate transistor through a first via over the gate of the pass-gate transistor, a first landing pad of the first metallization layer, and a second via over the first landing pad. A source/drain region of the pass-gate transistor is connected to the bit line of a third metallization layer through a contact over the source/drain region, a third via over the contact, a continuous via-plug over the third via, and a fourth via over the continuous via-plug. The continuous via-plug penetrates the first and second metallization layers.
1. A semiconductor structure, comprising:
a memory cell formed over a semiconductor substrate, comprising:
a latch circuit formed by two cross-coupled inverters; and
a pass-gate transistor coupling an output of the latch circuit to a bit line,
wherein each of the cross-coupled inverters is electrically connected to a VDD line formed in a first metallization layer,
wherein a word line formed in a second metallization layer is electrically connected to a gate of the pass-gate transistor through a first via over the gate of the pass-gate transistor, a first landing pad formed in the first metallization layer, and a second via over the first landing pad,
wherein a first source/drain region of the pass-gate transistor is electrically connected to the bit line formed in a third metallization layer through a contact over the first source/drain region, a third via over the contact, a continuous via-plug over the third via, and a fourth via over the continuous via-plug,
wherein the continuous via-plug penetrates the first and second metallization layers.
2. The semiconductor structure as claimed in claim 1 , wherein the third via and the continuous via-plug are formed of a single tungsten plug.
3. The semiconductor structure as claimed in claim 1 , wherein the contact has a rectangular shape, and a dimension ratio of a longer side to a shorter side of the contact is greater than 1.2.
4. The semiconductor structure as claimed in claim 1 , wherein the third via has a rectangular shape, and a dimension ratio of a longer side to a shorter side of the contact is greater than 1.2.
5. The semiconductor structure as claimed in claim 1 , wherein the continuous via-plug has an elliptical shape, and a dimension ratio of a longer axis to a shorter axis of the continuous via-plug is less than 1.2.
6. The semiconductor structure as claimed in claim 1 , wherein material of the continuous via-plug is selected from a group consisting of Ti, TiN, Pt, Co, Ru, W, TaN, Cu and a combination thereof.
7. The semiconductor structure as claimed in claim 1 , wherein the second via and the word line are made of the same material, the bit line and the fourth via are made of the same material, and the first and third vias, the VDD line and the first landing pad are made of different materials.
8. The semiconductor structure as claimed in claim 1 , wherein a second source/drain region of the pass-gate transistor is electrically connected to gate electrodes of one of the cross-coupled inverters through a local-connection layer that is coplanar and is made of the same metal material as the first and third vias.
9. A semiconductor structure, comprising:
a memory cell formed over a semiconductor substrate, comprising:
a latch circuit formed by two cross-coupled inverters; and
a pass-gate transistor coupling an output of the latch circuit to a bit line,
wherein each of the cross-coupled inverters is electrically connected to a VDD line formed in a first metallization layer,
wherein a word line formed in a second metallization layer is electrically connected to a gate of the pass-gate transistor through a first via over the gate of the pass-gate transistor, a first landing pad formed in the first metallization layer, and a second via over the first landing pad,
wherein a first source/drain region of the pass-gate transistor is electrically connected to the bit line formed in a third metallization layer through a contact over the first source/drain region, a third via over the contact, a first continuous via-plug over the third via, and a fourth via over the first continuous via-plug,
wherein the first continuous via-plug penetrates the first and second metallization layers; and
a logic cell comprising a transistor over the semiconductor substrate, wherein the transistor comprises:
a second source/drain region extending from a channel region,
wherein the second source/drain region is electrically connected to a power line through a fifth via over the second source/drain region, a second landing pad formed in the first metallization layer, a second continuous via-plug over the second landing pad, and a sixth via over the second continuous via-plug,
wherein the first continuous via-plug has a height that is greater than that of the second continuous via-plug.
10. The semiconductor structure as claimed in claim 9 , wherein the third via and the first continuous via-plug are formed of a single tungsten plug.
11. The semiconductor structure as claimed in claim 9 , wherein the word line and the second via are made of Cu-based material, and the first continuous via-plug is made of W-based material.
12. The semiconductor structure as claimed in claim 9 , wherein the word line and the second via are made of Co-based material, and the first continuous via-plug is made of W-based material.
13. The semiconductor structure as claimed in claim 9 , wherein the second via and the word line are made of the same material, the bit line, the power line and the fourth and sixth vias are made of the same material, and the first, third and fifth vias, the VDD line and the first and second landing pads are made of different materials.
14. The semiconductor structure as claimed in claim 9 , wherein a third source/drain region of the pass-gate transistor is electrically connected to gate electrodes of one of the cross-coupled inverters through a local-connection layer that is coplanar and is made of the same metal material as the first and third vias.
15. A semiconductor structure, comprising:
a memory cell formed over a semiconductor substrate, comprising:
a latch circuit formed by two cross-coupled inverters; and
a pass-gate transistor coupling an output of the latch circuit to a bit line,
wherein each of the cross-coupled inverters is electrically connected to a VDD line formed in a first metallization layer,
wherein a word line formed in a second metallization layer is electrically connected to a gate of the pass-gate transistor through a first via over the gate of the pass-gate transistor, a first landing pad formed in the first metallization layer, and a second via over the first landing pad,
wherein a first source/drain region of the pass-gate transistor is electrically connected to the bit line formed in a third metallization layer through a contact over the first source/drain region, a continuous via-plug over the first contact, and a third via over the continuous via-plug,
wherein the continuous via-plug penetrates the first and second metallization layers.
16. The semiconductor structure as claimed in claim 15 , wherein the continuous via-plug is formed of a single tungsten plug.
17. The semiconductor structure as claimed in claim 15 , wherein material of the continuous via-plug is selected from a group consisting of Ti, TiN, Pt, Co, Ru, W, TaN, Cu and a combination thereof.
18. The semiconductor structure as claimed in claim 15 , wherein the second via and the word line are made of the same material, the bit line and the third via are made of the same material, and the first via, the VDD line and the first landing pad are made of the same material.
19. The semiconductor structure as claimed in claim 15 , wherein the first contact has a rectangular shape, and a dimension ratio of a longer side to a shorter side of the first contact is greater than 1.2.
20. The semiconductor structure as claimed in claim 15 , wherein the first landing pad and the first via are made of Co-based metal material, and the bit line and the third via are made of Cu-based metal material.