Vector sum circuit and phase controller using the same
A vector sum circuit and a phase controller including the vector sum circuit are provided. The vector sum circuit includes an amplifier configured to amplify an input orthogonal signal by using a first metal oxide semiconductor field effect transistor (MOSFET), and a self body-biasing circuit comprising a resistor. The self body-biasing circuit is configured to connect a drain and a body of the first MOSFET to reduce a voltage connected to the body as a current at the drain increases.
1. A vector sum circuit comprising:
an amplifier configured to amplify an orthogonal signal by using a first metal oxide semiconductor field effect transistor (MOSFET);
a self body-biasing circuit comprising a resistor
configured to connect a drain and a body of the first MOSFET to reduce a voltage applied to the body as a current at the drain increases; and
an amplification controller configured to control a tail current of the amplifier,
wherein the amplifier controller comprises a second MOSFET and a switch, and
wherein the switch is configured to provide an output of a current mirror circuit interlocked with an output of a digital-to-analog converter (DAC) to a gate of the second MOSFET.
2. The vector sum circuit of claim 1 ,
wherein the amplification controller is further configured to
determine whether to enable the amplifier based on a phase difference to be controlled for the orthogonal signal.
3. The vector sum circuit of claim 2 , wherein the
second MOSFET is connected to a source of the first MOSFET and configured to control the tail current of the amplifier.
4. The vector sum circuit of claim 3 ,
wherein the first MOSFET is configured to receive the orthogonal signal through a gate thereof, and
wherein a drain of the second MOSFET is connected to the source of the first MOSFET.
5. The vector sum circuit of claim 2 ,
wherein the amplifier comprises:
a first amplifier; and
a second amplifier, and
wherein the amplification controller is further configured to control rates of a first tail current of the first amplifier and a second tail current of the second amplifier while maintaining a sum of the first tail current and the second tail current constant.
6. The vector sum circuit of claim 1 ,
wherein the orthogonal signal comprises an I+ signal, a Q+ signal, an I− signal, and a Q− signal,
wherein the amplifier comprises:
a first amplifier and a third amplifier into which the I+ signal and the I− signal are input, respectively, and
a second amplifier and a fourth amplifier into which the Q+ signal and the Q− signal are input, respectively,
wherein outputs of the first amplifier and the third amplifier are connected inversely with respect to each other, and
wherein outputs of the second amplifier and the fourth amplifier are connected inversely with respect to each other.
7. The vector sum circuit of claim 6 ,
wherein the first amplifier and the third amplifier comprise the first MOSFET into which the I+ signal is input and a third MOSFET into which the I− signal is input, respectively,
wherein the second amplifier and the fourth amplifier comprise a fourth MOSFET into which the Q+ signal is input and a fifth MOSFET into which the Q− signal is input, respectively,
wherein the first MOSFET and the third MOSFET are connected with a second MOSFET connected to a first output node of the current mirror circuit, and
wherein the fourth MOSFET and the fifth MOSFET are connected to a sixth MOSFET connected to a second output node of the current mirror circuit.