Laser-assisted device alteration using synchronized laser pulses
A pulsed-laser LADA system is provided, which utilizes temporal resolution to enhance spatial resolution. The system is capable of resolving CMOS pairs within the illumination spot using synchronization of laser pulses with the DUT clock. The system can be implemented using laser wavelength having photon energy above the silicon bandgap so as to perform single-photon LADA or wavelength having photon energy below the silicon bandgap so as to generate two-photon LADA. The timing of the laser pulses can be adjusted using two feedback loops tied to the clock signal of an ATE, or by adjusting the ATE's clock signal with reference to a fixed-pulse laser source.
1. A system for performing fault localization in a device-under-test (DUT), stimulated by a tester, the system comprising:
a laser source providing laser beam pulses having wavelength longer than 1107 nm, having energy selected such that total photon energy of photons arriving at a focal point generates electron-hole pairs, the pulses having a duration selected so as to induce two-photon absorption in the DUT about the focal point;
optical elements to receive the laser beam pulses and to direct the laser beam pulses onto the focal point;
a scanner for scanning the laser beam pulses over an area of interest in the DUT; and
timing electronics configured to receive a sync signal and a tester clock from the tester, the timing electronics controlling timing of the laser source according to the sync signal and with respect to transition of an edge of the tester clock, the tester being configured to output electrical test signals from the tester to the DUT selected to cause the DUT to generate electrical DUT output signals.
2. The system of claim 1 , wherein the total photon energy is set to be less than a DUT material bandgap.
3. The system of claim 1 , wherein the timing electronics times the laser beam pulses to vary delay or advance of signals propagating through the DUT.
4. The system of claim 1 , wherein the timing electronics times the laser beam pulses to push the DUT beyond a boundary condition.
5. The system of claim 1 , wherein the timing electronics vary the timing of the laser beam pulses so as to increase or decrease a switching time of the DUT to thereby determine severity of a fault within the DUT.
6. The system of claim 1 , wherein the laser beam pulses have a duration of about 100 fs.
7. The system of claim 1 , wherein the laser beam pulses have a wavelength of 1250 to 1550 nm.
8. The system of claim 1 , wherein the electrical test signals are selected to repeatedly stimulate the DUT at a pass/fail boundary.
9. The system of claim 1 , wherein the tester is configured to determine the marginal setting of the DUT by selecting at least one voltage and at least one frequency; and cause the electrical test signals to have the selected at least one voltage and the selected at least one frequency.
10. The system of claim 1 , wherein the tester is configured to determine voltage and frequency of the electrical test signals such that the DUT is just about to fail the test, or has just failed the test.
11. A method of performing fault localization in a device-under-test (DUT), stimulated by a tester, the system comprising:
by a laser source, providing laser beam pulses having wavelength longer than 1107 nm, having energy selected such that total photon energy of photons arriving at a focal point generates electron-hole pairs, the pulses having a duration selected so as to induce two-photon absorption in the DUT about the focal point;
with optical elements, receiving the laser beam pulses and directing the laser beam pulses onto the focal point;
by a scanner, scanning the laser beam pulses over an area of interest in the DUT; and
with timing electronics, receiving a sync signal and a tester clock from the tester, the timing electronics controlling timing of the laser source according to the sync signal and with respect to transition of an edge of the tester clock, the tester being configured to output electrical test signals from the tester to the DUT selected to cause the DUT to generate electrical DUT output signals.
12. The method of claim 11 , further comprising controlling the timing electronics to time the laser beam pulses to vary delay or advance of signals propagating through the DUT.
13. The method of claim 11 , further comprising controlling the timing electronics to time the laser beam pulses to push the DUT beyond a boundary condition.
14. The method of claim 11 , further comprising controlling the timing electronics to vary the timing of the laser beam pulses so as to increase or decrease a switching time of the DUT-to thereby determine severity of a fault within the DUT.
15. The method of claim 11 , wherein the laser beam pulses are of about 100 femtoseconds pulse width.
16. The method of claim 11 , wherein the laser beam pulses have a wavelength of 1250 to 1550 nm.
17. The method of claim 11 , further comprising, with a computer, visualizing pass/fail levels determined using the electrical DUT output signals in a graphical user interface.
18. The method of claim 11 , further comprising manufacturing an integrated circuit based on the electrical DUT output signals.
19. A computer for performing fault localization in a device-under-test (DUT), stimulated by a tester, the computer being situated to:
with a digital signal processor (DSP), control a laser source to provide laser beam pulses having wavelength longer than 1107 nm, having energy selected such that total photon energy of photons arriving at a focal point generates electron-hole pairs, the pulses having a duration selected so as to induce two-photon absorption in the DUT about the focal point, the laser beam pulses being received with optical elements to direct the laser beam pulses onto the focal point;
cause a scanner to scan the laser beam pulses over an area of interest in the DUT; and
cause timing electronics to receive a sync signal and a tester clock from the tester, the timing electronics controlling timing of the laser source according to the sync signal and with respect to transition of an edge of the tester clock, the tester being configured to output electrical test signals from the tester to the DUT selected to cause the DUT to generate electrical DUT output signals.
20. The computer of claim 17 , being further situated to control the timing electronics to time the laser beam pulses to vary delay or advance of signals propagating through the DUT.
21. The computer of claim 17 , being further situated to control the timing electronics to time the laser beam pulses to push the DUT beyond a boundary condition.
22. The computer of claim 17 , being further situated to control the timing electronics to vary the timing of the laser beam pulses so as to increase or decrease a switching time of the DUT-to thereby determine severity of a fault within the DUT.
23. The computer of claim 17 , being further situated to visualize pass/fail levels determined using the electrical DUT output signals in a graphical user interface.