Discrete three-dimensional processor
A discrete 3-D processor comprises first and second dice. The first die comprises three-dimensional memory (3D-M) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-M array(s). The first die does not comprise the off-die peripheral-circuit component. The first and second dice are communicatively coupled by a plurality of inter-die connections. The preferred discrete 3-D processor can be applied to mathematical computing, computer simulation, configurable gate array, pattern processing and neural network.
1. A discrete three-dimensional (3-D) processor, comprising:
a first die comprising a first semiconductor substrate and at least a three-dimensional memory (3D-M) array, wherein said 3D-M array comprises memory cells stacked above said first semiconductor substrate;
a second die comprising a second semiconductor substrate, at least a logic circuit and an off-die peripheral-circuit component of said 3D-M array, wherein said logic circuit and said off-die peripheral-circuit component comprise transistors disposed on said second semiconductor substrate;
wherein, said logic circuit processes data stored in said 3D-M array; said logic circuit is not a portion of a peripheral circuit of said 3D-M array; said first die does not comprise said off-die peripheral-circuit component; said first and second dice are communicatively coupled by a plurality of inter-die connections; said first and second semiconductor substrates are separate substrates.
2. The 3-D processor according to claim 1 , wherein:
said 3D-M array stores at least a portion of a look-up table (LUT) of a non-arithmetic function/model;
said logic circuit comprises an arithmetic logic circuit (ALC) for performing arithmetic operations on selected data from said LUT;
whereby said processor computes said non-arithmetic function/model, wherein said non-arithmetic function/model includes more operations than the arithmetic operations provided by said ALC.
3. The 3-D processor according to claim 2 , further comprising:
first and second 3D-M arrays in said first die, wherein said first 3D-M array stores at least a first portion of a first LUT of a first non-arithmetic function, said second 3D-M array stores at least a second portion of a second LUT of a second non-arithmetic function;
wherein said ALC performs arithmetic operations on selected data from said first or second LUT;
whereby said processor computes a combinational function, wherein said combinational function is a combination of said first and second non-arithmetic functions, said first and second non-arithmetic functions include more operations than the arithmetic operations provided by said ALC.
4. The 3-D processor according to claim 1 being a discrete 3-D configurable computing array, wherein:
said 3D-M array is a portion of a configurable computing element (CCE) and stores at least a portion of a look-up table (LUT) of a non-arithmetic function;
said logic circuit comprises at least a configurable logic element (CLE) and/or a configurable interconnect (CIT);
whereby said 3-D configurable computing array customizes said non-arithmetic function by programming said CCE and said CLE/CIT, wherein said non-arithmetic function includes more operations than the arithmetic operations provided by said CLE.
5. The 3-D processor according to claim 4 , further comprising:
first and second CCE's, wherein said first CCE comprises a first 3D-M array for storing at least a first portion of a first LUT of a first non-arithmetic function, said second CCE comprises a second 3D-M array for storing at least a second portion of a second LUT of a second non-arithmetic function, said first die comprises said first and second 3D-M arrays;
whereby said 3-D configurable computing array customizes a complex function by programming said CCE's and said CLE/CIT, wherein said complex function is a combination of said first and second non-arithmetic functions, said first and second non-arithmetic functions include more operations than the arithmetic operations provided by said CLE.
6. The 3-D processor according to claim 1 , wherein:
said processor comprises a plurality of storage-processing units (SPU's), each of said SPU's comprising said logic circuit and said 3D-M array; or,
said processor comprises a plurality of storage-processing units (SPU's), each of said SPU's comprising said logic circuit and at least two 3D-M arrays including said 3D-M array; or,
a first number of back-end-of-line (BEOL) layers of said first die is larger than a second number of BEOL layers of said second die; or,
a third number of address-line layers of said first die is at least twice as much as a fourth number of interconnect layers of said second die; or,
a fifth number of memory cells on each memory string in said first die is at least twice as much as a sixth number of interconnect layers of said second die; or,
a seventh number of interconnect layers in a substrate circuit of said first die is smaller than an eighth number of interconnect layers of said second die; or,
said 3D-M array comprises a plurality of vertically stacked memory cells without any semiconductor substrate therebetween; or,
said 3D-M array is a 3-D read-only memory (3D-ROM) array; or,
said 3D-M array is a non-volatile memory (NVM); or,
said 3D-M array is a 3-D writable memory (3D-W); or,
said 3D-M array is a 3-D printed memory (3D-P); or,
said 3D-M array is a horizontal 3D-M (3D-M H ) array; or,
said 3D-M array is a vertical 3D-M (3D-M V ) array; or,
said first and second dice are vertically stacked; or,
said first and second dice are face-to-face bonded; or,
the projection of said 3D-M array on said second die at least partially overlaps said logic circuit; or,
the pitch of said logic circuit is an integer multiple of the pitch of said 3D-M array; or,
the interconnects of said first die comprise tungsten; or,
the interconnects of said second die comprise copper; or,
said inter-die connections include bond wires, micro-bumps, through-silicon-vias (TSV's), and/or vertical interconnect access (VIA's).
7. A discrete three-dimensional (3-D) processor, comprising:
a first die comprising a first semiconductor substrate and at least a three-dimensional memory (3D-M) array, wherein said 3D-M array comprises memory cells stacked above said first semiconductor substrate;
a second die comprising a second semiconductor substrate, at least a processing circuit and an off-die peripheral-circuit component of said 3D-M array, wherein said processing circuit and said off-die peripheral-circuit component comprise transistors disposed on said second semiconductor substrate;
wherein, said processing circuit processes data stored in said 3D-M array; said processing circuit is not a portion of a peripheral circuit of said 3D-M array; said first die does not comprise said off-die peripheral-circuit component; said first and second dice are communicatively coupled by a plurality of inter-die connections; said first and second semiconductor substrates are separate semiconductor substrates.
8. The 3-D processor according to claim 7 being a discrete 3-D pattern processor, further comprising an input for transferring at least a first portion of a first pattern, wherein said 3D-M array stores at least a second portion of a second pattern, said processing circuit is a pattern-processing circuit for performing pattern processing for said first and second patterns.
9. The 3-D processor according to claim 8 being a discrete 3-D processor with an embedded search-pattern library, wherein said first pattern includes a target pattern, said second pattern includes a search pattern.
10. The 3-D processor according to claim 9 being a discrete information-security processor, wherein said input transfers at least a portion of data from a network packet or a computer file, said 3D-M array stores at least a portion of a virus pattern, said pattern-processing circuit searches said virus pattern in said portion of data.
11. The 3-D processor according to claim 9 being a discrete data-analysis processor, wherein said input transfers at least a portion of data from a database, said 3D-M array stores at least a portion of a keyword, said pattern-processing circuit searches said keyword in said portion of data.
12. The 3-D processor according to claim 9 being a discrete speech-recognition processor, wherein said input transfers at least a portion of audio data, said 3D-M array stores at least a portion of an acoustic/language model, said pattern-processing circuit performs speech recognition on said portion of audio data with said acoustic/language model.
13. The 3-D processor according to claim 9 being a discrete image-recognition processor, wherein said input transfers at least a portion of image data, said 3D-M array stores at least a portion of an image model, said pattern-processing circuit performs image recognition on said portion of image data with said image model.
14. The 3-D processor according to claim 8 being a discrete 3-D storage with in-situ pattern-processing capabilities, wherein said first pattern includes a search pattern, said second pattern includes a target pattern.
15. The 3-D processor according to claim 14 being a discrete anti-virus storage, wherein said input transfers at least a portion of a virus pattern, said 3D-M array stores at least a portion of data from a computer file, said pattern-processing circuit searches said virus pattern in said portion of data.
16. The 3-D processor according to claim 14 being a discrete searchable storage, wherein said input transfers at least a portion of a keyword, said 3D-M array stores at least a portion of data from a database, said pattern-processing circuit searches said keyword in said portion of data.
17. The 3-D processor according to claim 14 being a discrete searchable audio storage, wherein said input transfers at least a portion of an acoustic/language model, said 3D-M array stores at least a portion of audio data, said pattern-processing circuit performs speech recognition on said portion of audio data with said acoustic/language model.
18. The 3-D processor according to claim 14 being a discrete searchable image storage, wherein said input transfers at least a portion of an image model, said 3D-M array stores at least a portion of image data, said pattern-processing circuit performs image recognition on said portion of image data with said image model.
19. The 3-D processor according to claim 7 being a discrete 3-D neuro-processor, wherein said 3D-M array stores at least a portion of a synaptic weight, said processing circuit performs neural processing with said synaptic weight.
20. The 3-D processor according to claim 7 , wherein:
said processor comprises a plurality of storage-processing units (SPU's), each of said SPU's comprising said logic circuit and said 3D-M array; or,
said processor comprises a plurality of storage-processing units (SPU's), each of said SPU's comprising said logic circuit and at least two 3D-M arrays including said 3D-M array; or,
a first number of back-end-of-line (BEOL) layers of said first die is larger than a second number of BEOL layers of said second die; or,
a third number of address-line layers of said first die is at least twice as much as a fourth number of interconnect layers of said second die; or,
a fifth number of memory cells on each memory string in said first die is at least twice as much as a sixth number of interconnect layers of said second die; or,
a seventh number of interconnect layers in a substrate circuit of said first die is smaller than an eighth number of interconnect layers of said second die; or,
said 3D-M array comprises a plurality of vertically stacked memory cells without any semiconductor substrate therebetween; or,
said 3D-M array is a 3-D read-only memory (3D-ROM) array; or,
said 3D-M array is a non-volatile memory (NVM); or,
said 3D-M array is a 3-D writable memory (3D-W); or,
said 3D-M array is a 3-D printed memory (3D-P); or,
said 3D-M array is a horizontal 3D-M (3D-M H ) array; or,
said 3D-M array is a vertical 3D-M (3D-M V ) array; or,
said first and second dice are vertically stacked; or,
said first and second dice are face-to-face bonded; or,
the projection of said 3D-M array on said second die at least partially overlaps said processing circuit; or,
the pitch of said processing circuit is an integer multiple of the pitch of said 3D-M array; or,
the interconnects of said first die comprise tungsten; or,
the interconnects of said second die comprise copper; or,
said inter-die connections include bond wires, micro-bumps, through-silicon-vias (TSV's), and/or vertical interconnect access (VIA's).
21. A discrete three-dimensional (3-D) processor, comprising:
a plurality of storage-processing units (SPU's), each of said SPU's comprising at least a three-dimensional memory (3D-M) array, and a logic circuit, wherein said logic circuit processes data stored in said 3D-M array;
a first die comprising a first semiconductor substrate and said 3D-M array, wherein said 3D-M array comprises memory cells stacked above said first semiconductor substrate;
a second die comprising a second semiconductor substrate, said logic circuit and an off-die peripheral-circuit component of said 3D-M array, wherein said logic circuit and said off-die peripheral-circuit component comprise transistors disposed on said second semiconductor substrate;
wherein, said logic circuit is not a portion of a peripheral circuit of said 3D-M array; said first die does not comprise said off-die peripheral-circuit component; said first and second dice are communicatively coupled by a plurality of inter-die connections; said first and second semiconductor substrates are separate semiconductor substrates.
22. The 3-D processor according to claim 21 , wherein:
said 3D-M array stores at least a portion of a look-up table (LUT) of a non-arithmetic function/model;
said logic circuit comprises an arithmetic logic circuit (ALC) for performing arithmetic operations on selected data from said LUT;
whereby said processor computes said non-arithmetic function/model, wherein said non-arithmetic function/model includes more operations than the arithmetic operations provided by said ALC.
23. The 3-D processor according to claim 21 being a discrete 3-D configurable computing array, wherein:
said 3D-M array is a portion of a configurable computing element (CCE) and stores at least a portion of a look-up table (LUT) of a non-arithmetic function;
said logic circuit comprises at least a configurable logic element (CLE) and/or a configurable interconnect (CIT);
whereby said 3-D configurable computing array customizes said non-arithmetic function by programming said CCE and said CLE/CIT, wherein said non-arithmetic function includes more operations than the arithmetic operations provided by said CLE.
24. The 3-D processor according to claim 21 , wherein said logic circuit is a processing circuit.
25. The 3-D processor according to claim 24 , further comprising an input for transferring a first pattern, wherein said SPU's are communicatively coupled with said input, said 3D-M array stores a second pattern, said processing circuit performs pattern processing for said first and second patterns.
26. The 3-D processor according to claim 25 being a discrete 3-D processor with an embedded search-pattern library, wherein said first pattern includes a target pattern, said second pattern includes a search pattern.
27. The 3-D processor according to claim 25 being a discrete 3-D storage with in-situ pattern-processing capabilities, wherein said first pattern includes a search pattern, said second pattern includes a target pattern.
28. The 3-D processor according to claim 24 , wherein said 3D-M array stores at least a portion of a synaptic weight, said processing circuit performs neural processing with said synaptic weight.
29. The 3-D processor according to claim 21 , further comprising:
first and second 3D-M arrays, wherein said first 3D-M array stores at least a first portion of a look-up table (LUT) of an activation function, said second 3D-M array stores at least a second portion of a synaptic weight;
wherein said logic circuit comprises an arithmetic logic circuit (ALC) for performing arithmetic operations on selected data from said LUT and a neuro-processing circuit for performing neural processing with said synaptic weight.
30. The 3-D processor according to claim 21 , wherein:
each of said SPU's comprises at least two 3D-M arrays including said 3D-M array; or,
a first number of back-end-of-line (BEOL) layers of said first die is larger than a second number of BEOL layers of said second die; or,
a third number of address-line layers of said first die is at least twice as much as a fourth number of interconnect layers of said second die; or,
a fifth number of memory cells on each memory string in said first die is at least twice as much as a sixth number of interconnect layers of said second die; or,
a seventh number of interconnect layers in a substrate circuit of said first die is smaller than an eighth number of interconnect layers of said second die; or,
said 3D-M array comprises a plurality of vertically stacked memory cells without any semiconductor substrate therebetween; or,
said 3D-M array is a 3-D read-only memory (3D-ROM) array; or,
said 3D-M array is a non-volatile memory (NVM); or,
said 3D-M array is a 3-D writable memory (3D-W); or,
said 3D-M array is a 3-D printed memory (3D-P); or,
said 3D-M array is a horizontal 3D-M (3D-M H ) array; or,
said 3D-M array is a vertical 3D-M (3D-M V ) array; or,
said first and second dice are vertically stacked; or,
said first and second dice are face-to-face bonded; or,
the projection of said 3D-M array on said second die at least partially overlaps said logic circuit; or,
the pitch of said logic circuit is an integer multiple of the pitch of said 3D-M array; or,
the interconnects of said first die comprise tungsten; or,
the interconnects of said second die comprise copper; or,
said inter-die connections include bond wires, micro-bumps, through-silicon-vias (TSV's), and/or vertical interconnect access (VIA's).