Integrated isolation capacitance structure
Various capacitive isolation structures which can be readily incorporated into existing IC manufacturing procedures. An illustrative method embodiment for forming an isolation capacitance includes: (a) forming a recess on a surface of an integrated circuit substrate, the recess having a bottom surface; (b) coating the bottom surface with an insulating layer; (c) overlaying a bottom electrode on the insulating layer; (d) filling the recess with a bulk insulator having a minimum thickness no less than half a depth of the recess; and (e) depositing a top electrode above the bulk insulator.
1. A method for forming an isolation capacitance, comprising:
forming a recess on a surface of an integrated circuit substrate, the recess having a bottom surface;
coating the bottom surface with an insulating layer;
overlaying a bottom electrode on the insulating layer;
filling the recess with a bulk insulator having a minimum thickness no less than half a depth of the recess; and
depositing a top electrode above the bulk insulator.
2. The method of claim 1 , wherein the minimum thickness is no less than eighty percent of the depth of the recess.
3. The method of claim 1 , wherein the minimum thickness is no less than the depth of the recess.
4. The method of claim 1 , wherein the recess has at least one side wall coated with the insulating layer and overlaid by a sidewall portion of the bottom electrode, and wherein the top electrode is separated from the sidewall portion of the bottom electrode by no less than the minimum thickness.
5. The method of claim 4 , wherein the minimum thickness is 10 microns or more.
6. The method of claim 1 , wherein the recess has at least one flat, inclined corner surface coated with the insulating layer and overlaid by a corner portion of the bottom electrode, and wherein the top electrode is separated from the corner portion by no less than the minimum thickness.
7. The method of claim 1 , further comprising, prior to said forming: creating at least one transistor having a body well, a source region, a drain region, a gate dielectric, a gate, and an overlying dielectric layer.
8. The method of claim 7 , further comprising, prior to said depositing, patterning a metallization layer to provide:
an interconnect coupled to the at least one transistor; and
a bottom electrode interconnect that connects to the bottom electrode.
9. The method of claim 8 , further comprising, prior to said depositing:
protecting the metallization layer with an interlayer dielectric; and
planarizing the interlayer dielectric.
10. The method of claim 9 , wherein depositing the top electrode comprises patterning a metallization layer that includes the top electrode and a pin pad.
11. An isolation capacitor that comprises:
a recess on a surface of an integrated circuit substrate, the recess having a bottom surface at a depth below the surface of the integrated circuit substrate;
an insulating layer coating the bottom surface;
a bottom electrode overlaying the insulating layer;
a bulk insulator filling the recess above the bottom electrode, the bulk insulator having a minimum thickness no less than half of said depth; and
a top electrode deposited above the bulk insulator.
12. The isolation capacitor of claim 11 , wherein the minimum thickness is no less than eighty percent of the depth of the recess.
13. The isolation capacitor of claim 11 , wherein the minimum thickness is no less than the depth of the recess.
14. The isolation capacitor of claim 11 , wherein the recess has at least one side wall coated with the insulating layer and overlaid by a sidewall portion of the bottom electrode, and wherein the top electrode is separated from the sidewall portion of the bottom electrode by no less than the minimum thickness.
15. The isolation capacitor of claim 14 , wherein the minimum thickness is 10 microns or more.
16. The isolation capacitor of claim 11 , wherein the recess has at least one flat, inclined corner surface coated with the insulating layer and overlaid by a corner portion of the bottom electrode, and wherein the top electrode is separated from the corner portion by no less than the minimum thickness.
17. The isolation capacitor of claim 11 , wherein the substrate includes at least one transistor having a body well, a source region, a drain region, a gate dielectric, a gate, and an overlying dielectric layer.
18. The isolation capacitor of claim 17 , wherein the substrate has a patterned metallization layer that includes:
an interconnect coupled to the at least one transistor; and
a bottom electrode interconnect that connects to the bottom electrode.
19. The isolation capacitor of claim 18 , further including a planarized interlayer dielectric overlying the patterned metallization layer and the bulk insulator.
20. The isolation capacitor of claim 19 , wherein the top electrode is part of a second metallization layer overlying the planarized interlayer dielectric.