Integrated circuit including multi-height standard cell and method of designing the same
An integrated circuit includes a semiconductor substrate, first through third power rails, first through third selection gate lines, and a row connection wiring. The first through third power rails on the semiconductor substrate extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The first through third selection gate lines on the semiconductor substrate extend in the second direction over a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail, and are arranged sequentially in the first direction. The row connection wiring on the semiconductor substrate extends in the first direction to connect the first selection gate line and the third selection gate line.
1. An integrated circuit, comprising:
a semiconductor substrate;
a first power rail, a second power rail, and a third power rail extending in a first direction and arranged sequentially in a second direction perpendicular to the first direction on the semiconductor substrate;
a first selection gate line, a second selection gate line, and a third selection gate line extending in the second direction over a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail, and arranged sequentially in the first direction; and
a row connection wiring extending in the first direction to connect the first selection gate line and the third selection gate line, wherein:
the second selection gate line connects first gate electrodes of selection transistors in the first region and second gate electrodes of selection transistors in the second region, the first gate electrodes corresponding to a portion of the second selection gate line and the second gate electrodes corresponding to another portion of the second selection gate line.
2. The integrated circuit as claimed in claim 1 , wherein:
the first selection gate line, the third selection gate line, and the row connection wiring form a first selection node receiving a first selection signal, and
the second selection gate line serves as a second selection node receiving a second selection signal.
3. The integrated circuit as claimed in claim 1 , wherein the second selection gate line is not cut by a gate cut area in the first and second regions.
4. The integrated circuit as claimed in claim 1 , wherein the first selection gate line connects a first gate electrode of a selection transistor in the first region and a second gate electrode of a selection transistor in the second region, the first gate electrode corresponding to a portion of the first selection gate line and the second gate electrode corresponding to another portion of the first selection gate line.
5. The integrated circuit as claimed in claim 1 , wherein the third selection gate line is cut by a gate cut area into a first gate segment corresponding to a first gate electrode of a selection transistor in the first region and a second gate segment corresponding to a second gate electrode of a selection transistor in the second region.
6. The integrated circuit as claimed in claim 5 , further comprising a column connection wiring extending in the second direction to connect the first gate segment of the third selection gate line and the second gate segment of the third selection gate line.
7. The integrated circuit as claimed in claim 1 , wherein the third selection gate line connects a first gate electrode of a selection transistor in the first region and a second gate electrode of a selection transistor in the second region, the first gate electrode corresponding to a portion of the third selection gate line and the second gate electrode corresponding to another portion of the third selection gate line.
8. The integrated circuit as claimed in claim 1 , further comprising:
a first multiplexer in the first region, the first multiplexer to select one of a first input signal and a second input signal based on a first selection signal and a second selection signal to output a first output signal; and
a second multiplexer in the second region, the second multiplexer to select one of a third input signal and a fourth input signal based on the first selection signal and the second selection signal to output a second output signal.
9. The integrated circuit as claimed in claim 8 , wherein:
the first multiplexer includes a first output wiring in a metal layer and configured to provide the first output signal, and
a column extending portion of the first output wiring is over the first selection gate line or the third selection gate line along the first selection gate line or the third selection gate line.
10. The integrated circuit as claimed in claim 8 , wherein:
the second multiplexer includes a second output wiring in a first metal layer and configured to provide the second output signal, and
a column extending portion of the second output wiring is over the second selection gate line along the second selection gate line.
11. The integrated circuit as claimed in claim 10 , wherein the row connection wiring is in a second metal layer over the first metal layer.
12. The integrated circuit as claimed in claim 10 , wherein the row connection wiring crosses the column extending portion of the second output wiring at a right angle.
13. The integrated circuit as claimed in claim 8 , wherein:
the first multiplexer includes:
a first selection transistor controlled by an inverted voltage level of the second selection signal to pull up a first output node generating the first output signal;
a second selection transistor to be gated by a voltage level of the first selection signal to pull down the first output node;
a third selection transistor to be gated by an inverted voltage level of the first selection signal to pull up the first output node; and
a fourth selection transistor to be gated by a voltage level of the second selection signal to pull down the first output node, and wherein the second multiplexer includes:
a fifth selection transistor to be gated by the inverted voltage level of the second selection signal to pull up a second output node generating the second output signal;
a sixth selection transistor to be gated by the voltage level of the first selection signal to pull down the second output node;
a seventh selection transistor to be gated by the inverted voltage level of the first selection signal to pull up the second output node; and
an eighth selection transistor to be gated by the voltage level of the second selection signal to pull down the second output node.
14. The integrated circuit as claimed in claim 13 , wherein:
the first selection gate line serves as gate electrodes of the second selection transistor and the sixth selection transistor,
the second selection gate line serves as gate electrodes of the first selection transistor, the fourth selection transistor, the fifth selection transistor and the eighth selection transistor, and
the third selection gate line serves as gate electrodes of the third selection transistor and the seventh selection transistor.
15. The integrated circuit as claimed in claim 14 , wherein the row connection wiring connects the gate electrode of the sixth selection transistor and the gate electrode of the seventh selection transistor.
16. The integrated circuit as claimed in claim 14 , wherein:
the first selection transistor, the third selection transistor, the fifth selection transistor, and the seventh selection transistor are first-type transistors, and
the second selection transistor, the fourth selection transistor, the sixth selection transistor, and the eighth selection transistor are second-type transistors.
17. An integrated circuit, comprising:
a first selection transistor to be gated by an inverted voltage level of a second selection signal to pull up a first output node;
a second selection transistor to be gated by a voltage level of a first selection signal to pull down the first output node;
a third selection transistor to be gated by an inverted voltage level of the first selection signal to pull up the first output node;
a fourth selection transistor to be gated by a voltage level of the second selection signal to pull down the first output node,
a fifth selection transistor to be gated by the inverted voltage level of the second selection signal to pull up a second output node;
a sixth selection transistor to be gated by the voltage level of the first selection signal to pull down the second output node;
a seventh selection transistor to be gated by the inverted voltage level of the first selection signal to pull up the second output node;
an eighth selection transistor to be gated by the voltage level of the second selection signal to pull down the second output node;
a first selection gate line serving as gate electrodes of the second selection transistor and the sixth selection transistor;
a second selection gate line serving as gate electrodes of the first selection transistor, the fourth selection transistor, the fifth selection transistor, and the eighth selection transistor;
a third selection gate line serving as gate electrodes of the third selection transistor and the seventh selection transistor; and
a row connection wiring connecting the first selection gate line and the third selection gate line.
18. The integrated circuit as claimed in claim 17 , wherein:
the first output node and the second output node include wirings in a first metal layer, and
the row connection wiring is in a second metal layer different from the first metal layer.
19. An integrated circuit, comprising:
a semiconductor substrate;
a first power rail, a second power rail, and a third power rail extending in a first direction and arranged sequentially in a second direction perpendicular to the first direction on the semiconductor substrate;
a first selection gate line, a second selection gate line, and a third selection gate line extending in the second direction over a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail, and arranged sequentially in the first direction;
a row connection wiring extending in the first direction to connect the first selection gate line and the third selection gate line;
a first multiplexer in the first region, the first multiplexer to select one of a first input signal and a second input signal based on a first selection signal and a second selection signal to output a first output signal; and
a second multiplexer in the second region, the second multiplexer to select one of a third input signal and a fourth input signal based on the first selection signal and the second selection signal to output a second output signal.