Error correction code memory device and codeword accessing method thereof

1. A codeword accessing method, comprising:

receiving a write data with M message bits;

generating parity information with N-M bits based on an error correction algorithm and the M message bits;

providing a random number generator to generate an internal data;

transforming the M message bits and the parity information to a scrambled codeword with N bits by a scrambling operation according to the internal data; and

writing the scrambled codeword into a memory device,

wherein the scrambled codeword is scrambled in a codeword bit sequence.

2. The codeword accessing method as claimed in claim 1 , wherein the scrambled codeword is an extended codeword, and a syndrome of the extended codeword is 0 if there are no error bits in the scrambled codeword.

3. The codeword accessing method as claimed in claim 1 , wherein the parity information is generated by operating the error correction algorithm based on a modified BCH code, a modified Hamming code or a modified Hsiao code.

4. The codeword accessing method as claimed in claim 1 , wherein the scrambling operation is a linear transformation operation or a non-linear transformation operation.

5. The codeword accessing method as claimed in claim 1 , further comprising:

receiving an accessed address of the memory device; and

transforming the M message bits and the parity information to the scrambled codeword by the scrambling operation according to the accessed address.

6. The codeword accessing method as claimed in claim 1 , further comprising:

reading a device identification of the memory device; and

transforming the M message bits and the parity information to the scrambled codeword by the scrambling operation according to the identification of the memory device.

7. The codeword accessing method as claimed in claim 1 , further comprising:

reading a configuration value from a configurable status register of the memory device; and

transforming the M message bits and the parity information to the scrambled codeword by the scrambling operation according to the configuration value.

8. The codeword accessing method as claimed in claim 1 , wherein a data format of the scrambled codeword is adjusted according to an external command.

9. The codeword accessing method as claimed in claim 1 , further comprising:

receiving an external data from an external electronic apparatus; and

transforming the M message bits and the parity information to the scrambled codeword by the scrambling operation according to the external data.

10. The codeword accessing method as claimed in claim 1 , further comprising:

providing a lookup table for operating the scrambling operation.

11. The codeword accessing method as claimed in claim 1 , further comprising:

reading the scrambled codeword from the memory device to obtain a readout codeword;

checking syndromes of the readout codeword;

performing descrambling operation on the readout codeword to obtain a correct scrambled information with N bits; and

operating an error correction operation on the correct scrambled information based on the error correction algorithm to obtain readout data with M bits.

12. The codeword accessing method as claimed in claim 1 , wherein the scrambled codeword includes at least one flip bit.

13. The codeword accessing method as claimed in claim 1 , further comprising:

scrambling the M message bits to generate scrambled message with M bits before the parity information has been generated; and

generating the parity information based on the error correction algorithm and the scrambled message.

14. A codeword accessing method, comprising:

receiving a write data with M message bits;

scrambling the M message bits to generate a scrambled message with M bits according to an internal data generated by a random number generator before parity information has been generated;

generating the parity information with N-M bits based on an error correction algorithm and the scrambled message;

combining the scrambled message and the parity information to form a scrambled codeword with N bits; and

writing the scrambled codeword into a memory device.

15. The codeword accessing method as claimed in claim 14 , further comprising:

reading the scrambled codeword from the memory device to obtain a readout codeword;

checking syndromes of the readout codeword;

operating an error correction operation on the readout codeword based on the error correction algorithm to obtain a correct scrambled information with N bits; and

performing descrambling operation on the correct scrambled information to obtain readout data with M bits.

16. An error correction code memory device, comprising:

a memory array;

a plurality of sense amplifiers and a plurality of write drivers, coupled to the memory array; and

a control logic circuit, coupled to the sense amplifiers and the write drivers, where the control logic circuit is configured to:

receive a write data with M message bits;

generate parity information with N-M bits based on an error correction algorithm and the M message bits, where N and M are positive integers, and N is larger than M;

transform the M message bits and the parity information to a scrambled codeword with N bits by a scrambling operation according to an internal data generated by a random number generator, where the scrambled codeword contains only a part of the M message bits; and

write the scrambled codeword into a memory device,

wherein the scrambled codeword is scrambled in a codeword bit sequence.

17. The error correction code memory device as claimed in claim 16 , wherein the control logic circuit is further configured to:

read the scrambled codeword from the memory device to obtain a readout codeword;

check syndromes of the readout codeword;

perform descrambling operation on the readout codeword to obtain a correct scrambled information with N bits; and

operate an error correction operation on the correct scrambled information based on the error correction algorithm to obtain readout data with M bits.

18. The error correction code memory device as claimed in claim 16 , wherein the control logic circuit is further configured to:

scramble the M message bits to generate scrambled message with M bits before the parity information has been generated; and

generate the parity information based on the error correction algorithm and the scrambled message.

19. An error correction code memory device, comprising:

a memory array;

a plurality of sense amplifiers and a plurality of write drivers, coupled to the memory array; and

a control logic circuit, coupled to the sense amplifiers and the write drivers, where the control logic circuit is configured to:

receiving a write data with M message bits;

scrambling the M message bits to generate a scrambled message with M bits according to an internal data generated by a random number generator before parity information has been generated;

generating the parity information with N-M bits based on an error correction algorithm and the scrambled message;

combining the scrambled message and the parity information to form a scrambled codeword with N bits; and

writing the scrambled codeword into a memory device.

20. The error correction code memory device as claimed in claim 19 , wherein the control logic circuit is further configured to:

read the scrambled codeword from the memory device to obtain a readout codeword;

check syndromes of the readout codeword;

operate an error correction operation on the readout codeword based on the error correction algorithm to obtain a correct scrambled information with N bits; and

perform descrambling operation on the correct scrambled information to obtain readout data with M bits.