Fabricating method of fin structure with tensile stress and complementary FinFET structure
A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.
1. A fabricating method of a fin structure with tensile stress, comprising:
providing a substrate comprising an N-type transistor region and a P-type transistor region;
forming two first trenches and two second trenches within the substrate, wherein the first trenches define a fin structure, and the second trenches segment the first trenches;
performing a flowable chemical vapor deposition process to form a silicon oxide layer in the first trenches and the second trenches;
planarizing the silicon oxide layer, wherein after planarizing the silicon oxide layer, a top surface of the silicon oxide layer is not lower than a top surface of the fin structure;
forming a patterned mask layer only within the N-type transistor region, wherein the patterned mask layer only overlaps the silicon oxide layer within the second trenches;
removing part of the silicon oxide layer by taking the patterned mask layer as a mask to make both the top surface of the silicon oxide layer in the first trenches within the N-type transistor region and the top surface of the silicon oxide layer within the P-type transistor region lower than the top surface of the fin structure; and
removing the patterned mask layer.
2. The fabricating method of a fin structure with tensile stress of claim 1 , wherein:
after planarizing the silicon oxide layer and before forming the patterned mask layer, the top surface of the silicon oxide layer is higher than the top surface of the fin structure; and
after removing the patterned mask layer, the top surface of the silicon oxide layer within the second trenches within the N-type transistor region is higher than the top surface of the fin structure.
3. The fabricating method of a fin structure with tensile stress of claim 1 , wherein:
after planarizing the silicon oxide layer and before forming the patterned mask layer, the top surface the silicon oxide layer is aligned with the top surface of the fin structure; and
after removing the patterned mask layer, the top surface of the silicon oxide layer within the second trenches within the N-type transistor region is aligned with the top surface of the fin structure.
4. The fabricating method of a fin structure with tensile stress of claim 1 , wherein the patterned mask layer is not formed within the P-type transistor region.
5. The fabricating method of a fin structure with tensile stress of claim 4 , wherein the top surface of the silicon oxide layer in the second trenches within the P-type transistor region is aligned with the silicon oxide layer in the first trenches within the P-type transistor region.