IP Library › Granted Patent US 10,964,279
Granted Patent B2
US 10,964,279 · App. 16/253,769 · Granted Mar 30, 2021

Display driver, electrooptic device, and electronic apparatus

Inventor: Ryota Bansho (Matsumoto, JP)
Assignee: SEIKO EPSON CORPORATION
G09G3/3622G02F1/13306G09G3/2092G09G3/3258G09G2310/0251G09G2310/0291G09G2310/0297
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,964,279
App. No.
16/253,769
Granted
Mar 30, 2021
Kind
B2
Abstract

A display driver includes an amplifier circuit configured to output time-sequentially arrayed first to n-th data voltages to an image-signal input terminal, and a switch-control-signal output circuit configured to output switch control signals that control the first to n-th switches disposed between the image-signal input terminal and respective first to n-th data lines. The switch-control-signal output circuit outputs the switch control signals that turn on two or more switches including a p-th switch (where p is an integer within the range of 2 to n, inclusive) among the first to n-th switches during a first driving period. The amplifier circuit outputs a p-th data voltage among the first to n-th data voltages during the first driving period.

Claims (42)

1. A display driver comprising:

an amplifier circuit configured to output, in time series, first to n-th data voltages to an image-signal input terminal of an electro-optic panel during first to n-th driving periods in a first horizontal scanning period, where n represents an integer of 4 or more; and

a switch-control-signal output circuit configured to:

output switch control signals for controlling first to n-th switches disposed between the image-signal input terminal of the electro-optic panel and respective first to n-th data lines, including a p-th switch different from the first switch among the first to n-th switches, where p represents an integer within the range of 3 to n−1, inclusive;

output the switch control signals that turn on the first switch connected between the image-signal input terminal and the first data line, and a first other switch among the first switch to a (p−1)th switch connected between the image-signal input terminal and its corresponding data line, during the first driving period among the first to n-th driving periods; and

output the switch control signals that turn on the p-th switch connected between the image-signal input terminal and the p-th data line, and a second other switch among the p-th switch to the n-th switch connected between the image-signal input terminal and its corresponding data line, during a p-th driving period among the first to n-th driving periods,

wherein the amplifier circuit is configured to output:

the first data voltage fed to the first data line, among the first to n-th data voltages, during the first driving period to the first data line and the first other data line; and

a p-th data voltage fed to the p-th data line, among the first to n-th data voltages, during the p-th driving period to the p-th data line and the second other data line;

wherein the switch-control-signal output circuit is configured to:

output the switch control signals that turn on the first to (p−1)th switches connected between the image-signal input terminal and the first to (p−1)th data lines, respectively, during the first driving period; and

output the switch control signals that turn on the p-th to n-th switches connected between the image-signal input terminal and the p-th to n-th data lines, respectively, during the p-th driving period, and

the amplifier circuit is configured to:

output the first data voltage, fed to the first data line, to the first to (p−1)th data lines during the first driving period; and

output the p-th data voltage, fed to the p-th data line, to the p-th to n-th data lines during the p-th driving period.

2. The display driver according to claim 1 , wherein

the switch-control-signal output circuit is configured to output the switch control signals for turning on two or more of the switches including the p-th switch during the first driving period in a second horizontal scanning period subsequent to the first horizontal scanning period, and

the amplifier circuit is configured to output the p-th data voltage among the first to n-th data voltages during the first driving period.

3. The display driver according to claim 1 , wherein

the switch-control-signal output circuit is configured to output the switch control signals for turning on the first to n-th switches during the first driving period, and

the switch-control-signal output circuit is configured to output the switch control signals for turning on an i-th switch, where i represents an integer within the range of 2 to n, inclusive, among the first to n-th switches and turning off the switches other than the i-th switch during an i-th driving period among the first to n-th driving periods.

4. The display driver according to claim 3 , wherein a length of the first driving period is larger than a length of the i-th driving period.

5. The display driver according to claim 1 , wherein

the switch-control-signal output circuit is configured to output the switch control signals for turning on the first to k-th switch, among the first to n-th switches during the first driving period, where k represents an integer within the range of 2 to n−2, inclusive,

the switch-control-signal output circuit is configured to output the switch control signals for turning on k+1-th to q-th switches among the first to n-th switches during a (k+1)th driving period among the first to n-th driving periods, where q represents an integer within the range of k+2 to n, inclusive, and

the amplifier circuit is configured to output a (k+1)th data voltage among the first to n-th data voltages during the (k+1)th driving period.

6. The display driver according to claim 1 , wherein

the switch-control-signal output circuit is configured to output the switch control signals for turning on an r-th and (r+1)th switches during an r-th driving period among the first to n-th driving periods, where r represents an integer within the range of 1 to n−1, inclusive, and

the amplifier circuit is configured to output an r-th data voltage among the first to n-th data voltages during the r-th driving period.

7. The display driver according to claim 1 , further comprising:

a D/A converter circuit configured to D/A-convert the first to n-th display data and output time-divided first to n-th D/A converted voltages,

wherein the amplifier circuit is configured to output the first to n-th data voltages corresponding to the time-divided first to n-th D/A converted voltage during the first to n-th driving periods, respectively.

8. The display driver according to claim 1 , wherein

the amplifier circuit is configured to output the first to n-th data voltages having a positive or negative polarity in the horizontal scanning period, and

the amplifier circuit is configured to output the first to n-th data voltages having the other one of the positive and negative polarities in a second horizontal scanning period one frame after the first horizontal scanning period.

9. An electronic apparatus comprising:

the display driver according to claim 1 ; and

an electro-optic panel driven by the display driver.

10. An electronic apparatus comprising:

the display driver according to claim 1 .

11. The display driver according to claim 1 , wherein a length of the first driving period is longer than lengths of the second to n-th driving periods.

12. The display driver according to claim 1 , wherein n represents a total number of driving periods in the first horizontal scanning period.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 22, 2019
From: BANSHO, RYOTA
To: SEIKO EPSON CORPORATION
Reel/Frame 048090/0716 →
Priority Claims (1)
JP JP2018-008553 · Jan 23, 2018 · national
Continuity (1)
Related Publication 20190228725A1 · Jul 25, 2019