IP Library Granted Patent US 11,987,874
Granted Patent B2
US 11,987,874 · App. 16/254,904 · Granted May 21, 2024

Backside metal formation methods and systems

Inventor: Michael J. Seddon (Gilbert, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
C23C14/18C23C14/243C23C14/5873
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,987,874
App. No.
16/254,904
Granted
May 21, 2024
Kind
B2
Abstract

Implementations of methods of forming a metal layer on a semiconductor wafer may include: placing a semiconductor wafer into an evaporator dome and adding a material to a crucible located a predetermined distance from the semiconductor wafer. The semiconductor wafer may include an average thickness of less than 39 microns. The method may also include heating the material in the crucible to a vapor and depositing the material on a second side of the semiconductor wafer.

Claims (32)

1. A method of forming a metal layer on a semiconductor wafer, the method comprising:

placing a semiconductor wafer into an evaporator dome, the semiconductor wafer comprising an average thickness of less than 39 microns;

adding a material to a crucible located a predetermined distance from the semiconductor wafer;

heating the material in the crucible to a vapor; and

depositing the material on a second side of the semiconductor wafer.

2. The method of claim 1 , wherein heating comprises one of resistive heating or electron beam heating.

3. The method of claim 1 , wherein the semiconductor wafer comprises a plurality of die on a first side of the semiconductor wafer.

4. The method of claim 1 , wherein the semiconductor wafer comprises an edge support ring around a perimeter of the semiconductor wafer.

5. The method of claim 1 , wherein a first side of the semiconductor wafer is coupled to a backgrinding tape.

6. The method of claim 1 , wherein a first side of the semiconductor wafer is not coupled to a backgrinding tape.

7. The method of claim 1 , wherein the material in the crucible is a metal comprising one of titanium, gold, copper, tin, tungsten, aluminum, silver, nickel, chromium, or any combination thereof.

8. The method of claim 1 , the method further comprising etching the semiconductor wafer, wherein etching comprises wet chemical etching.

9. The method of claim 1 , wherein the semiconductor wafer is not coupled to a carrier.

10. A method of forming a metal layer on a semiconductor wafer, the method comprising:

placing a semiconductor wafer into an evaporator dome, the semiconductor wafer comprising a first side and a second side;

adding a material to a crucible located a predetermined distance from the semiconductor wafer; and

coupling the material with the second side of the semiconductor wafer through heating;

wherein heating comprises one of resistive heating or electron beam heating; and

wherein the semiconductor wafer comprises an average thickness of less than 10 microns.

11. The method of claim 10 , wherein the semiconductor wafer comprises an edge ring around a perimeter of the semiconductor wafer.

12. The method of claim 10 , wherein the first side of the semiconductor wafer is coupled to a backgrinding tape.

13. The method of claim 10 , wherein the material in the crucible is a metal comprising one of titanium, gold, copper, tin, tungsten, aluminum, silver, nickel, chromium, or any combination thereof.

14. The method of claim 10 , the method further comprising etching the semiconductor wafer, wherein etching comprises wet chemical etching.

15. The method of claim 10 , wherein the semiconductor wafer is not coupled to a carrier.

16. A method of forming a metal layer on a semiconductor wafer, the method comprising:

placing a semiconductor wafer into an evaporator dome, the semiconductor wafer comprising an average thickness between 5 microns and 39 microns;

coupling a material with a second side of the semiconductor wafer through heating;

wherein heating comprises one of resistive heating or electron beam heating; and

wherein the semiconductor wafer comprises an edge ring around a perimeter of the semiconductor wafer.

17. The method of claim 16 , wherein the average thickness of the semiconductor wafer is 25 microns.

18. The method of claim 16 , wherein a first side of the semiconductor wafer is coupled to a backgrinding tape.

19. The method of claim 16 , the method further comprising etching the semiconductor wafer, wherein etching comprises wet chemical etching.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 049473, FRAME 0932 Recorded Aug 17, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064618/0721 →
SECURITY INTEREST Recorded Jun 14, 2019
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 049473/0932 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 23, 2019
From: SEDDON, MICHAEL J.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 048107/0482 →
Continuity (1)
Related Publication 20200232086A1 · Jul 23, 2020