IP Library › Granted Patent US 10,979,658
Granted Patent B2
US 10,979,658 · App. 16/255,679 · Granted Apr 13, 2021

Imaging device

Inventors: Takayoshi Yamada (Hyogo, JP); Yasuo Miyake (Osaka, JP); Masashi Murakami (Kyoto, JP)
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
H04N5/363H01L27/14612H01L27/14665H04N5/351H04N5/353H04N5/3575H04N5/374H04N5/378H04N5/37452
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Quick Facts
Patent No.
US 10,979,658
App. No.
16/255,679
Granted
Apr 13, 2021
Kind
B2
Abstract

An imaging device according to the present disclosure includes a photoelectric converter that converts light into an electric charge; a transfer transistor; a charge accumulation node coupled to the photoelectric converter via the transfer transistor; a first signal detection transistor having a gate coupled to the charge accumulation node; a first reset transistor one of a source and a drain of which is coupled to the charge accumulation node; and a second reset transistor one of a source and a drain of which is coupled to the photoelectric converter, wherein one of a source and a drain of the first signal detection transistor is coupled to the other of the source and the drain of the first reset transistor and the other of the source and drain of the second reset transistor.

Claims (56)

1. An imaging device comprising:

a photoelectric converter that converts light into an electric charge;

a transfer transistor;

a charge accumulation node coupled to the photoelectric converter via the transfer transistor;

a first signal detection transistor having a gate coupled to the charge accumulation node;

a signal line coupled to one of a source and a drain of the first signal detection transistor but not through either a gate or the other of the source and the drain of the first signal detection transistor, a signal corresponding to an electric potential of the charge accumulation node being transmitted through the signal line;

a first reset transistor one of a source and a drain of which is coupled to the charge accumulation node; and

a second reset transistor one of a source and a drain of which is coupled to the photoelectric converter, wherein

the one of the source and the drain of the first signal detection transistor is coupled to the other of the source and the drain of the first reset transistor and the other of the source and drain of the second reset transistor but not through either the gate or the other of the source and the drain of the first signal detection transistor, and

no transistor other than the transfer transistor is coupled, in series with the transfer transistor, between the photoelectric converter and the gate of the first signal detection transistor.

2. The imaging device according to claim 1 , wherein at least a part of a signal output by the first signal detection transistor is fed back to the other of the source and drain of the first reset transistor and the other of the source and drain of the second reset transistor.

3. The imaging device according to claim 1 , further comprising:

a feedback transistor coupled between the one of the source and the drain of the first signal detection transistor and the other of the source and drain of the first reset transistor;

a first capacitor having a first end and a second end, the first end being coupled to the charge accumulation node, the second end being coupled to the other of the source and drain of the first reset transistor; and

a second capacitor having a third end and a fourth end, the third end being coupled to a node between the first reset transistor and the feedback transistor.

4. The imaging device according to claim 1 , further comprising:

a feedback transistor one of a source and a drain of which is coupled to the one of the source and drain of the first signal detection transistor;

a first capacitor having a first end and a second end, the first end being coupled to the charge accumulation node, the second end being coupled to the other of the source and drain of the feedback transistor; and

a second capacitor having a third end and a fourth end, the third end being coupled to a node between the feedback transistor and the first capacitor.

5. The imaging device according to claim 1 , further comprising a buffer circuit coupled between the transfer transistor and the one of the source and the drain of the second reset transistor.

6. The imaging device according to claim 1 , further comprising a power line couple to the other of the source and the drain of the first signal detection transistor, at least two different voltages being selectively applied to the power line.

7. The imaging device according to claim 1 , wherein the one of the source and the drain of the second reset transistor is coupled to a node between the photoelectric converter and the transfer transistor.

8. The imaging device according to claim 1 , wherein

the photoelectric converter includes a first electrode, a second electrode, and a photoelectric conversion layer that is sandwiched between the first electrode and the second electrode.

9. An imaging device comprising:

a photoelectric converter that converts incident light into an electric charge;

a transfer transistor;

a charge accumulation node coupled to the photoelectric converter via the transfer transistor;

a first signal detection transistor having a gate coupled to the charge accumulation node;

a second signal detection transistor having a gate coupled to the photoelectric converter;

a signal line coupled to one of a source and a drain of the first signal detection transistor but not through either a gate or the other of the source and the drain of the first signal detection transistor, a signal corresponding to an electric potential of the charge accumulation node being transmitted through the signal line;

a first reset transistor one of a source and a drain of which is coupled to the charge accumulation node; and

a second reset transistor one of a source and a drain of which is coupled to the photoelectric converter, wherein

the one of the source and the drain of the first signal detection transistor is coupled to the other of the source and drain of the first reset transistor but not through either the gate or the other of the source and the drain of the first signal detection transistor,

one of a source and a drain of the second signal detection transistor is coupled to the other of the source and drain of the second reset transistor, and

no transistor is coupled between the photoelectric converter and the gate of the second signal detection transistor.

10. The imaging device according to claim 9 , wherein

at least a part of a signal output by the first signal detection transistor is fed back to the other of the source and drain of the first reset transistor; and

at least a part of a signal output by the second signal detection transistor is fed back to the other of the source and drain of the second reset transistor.

11. The imaging device according to claim 9 , further comprising:

a feedback transistor coupled between the one of the source and drain of the first signal detection transistor and the other of the source and drain of the first reset transistor;

a first capacitor having a first end and a second end, the first end being coupled to the charge accumulation node, the second end being coupled to the other of the source and drain of the first reset transistor; and

a second capacitor having a third end and a fourth end, the third end being coupled to a node between the first reset transistor and the feedback transistor.

12. The imaging device according to claim 9 , further comprising:

a feedback transistor one of a source and a drain of which is coupled to the one of the source and drain of the first signal detection transistor;

a first capacitor having a first end and a second end, the first end being coupled to the charge accumulation node, the second end being coupled to the other of the source and the drain of the feedback transistor; and

a second capacitor having a third end and a fourth end, the third end being coupled to a node between the feedback transistor and the first capacitor.

13. The imaging device according to claim 9 , further comprising a buffer circuit coupled between the transfer transistor and the one of the source and the drain of the second reset transistor.

14. The imaging device according to claim 9 , wherein the one of the source and the drain of the second signal detection transistor is coupled to the signal line.

15. The imaging device according to claim 9 , further comprising a power line couple to the other of the source and the drain of the first signal detection transistor, at least two different voltages being selectively applied to the power line.

16. The imaging device according to claim 15 , wherein the other of the source and the drain of the second signal detection transistor is coupled to the power line.

17. The imaging device according to claim 9 , wherein

the one of the source and the drain of the second signal detection transistor is coupled to the signal line but not through either the gate or the other of the source and the drain of the second signal detection transistor, and

the one of the source and the drain of the second signal detection transistor is coupled to the other of the source and drain of the second reset transistor but not through either the gate or the other of the source and the drain of the second signal detection transistor.

18. The imaging device according to claim 9 , wherein

the photoelectric converter includes a first electrode, a second electrode, and a photoelectric conversion layer that is sandwiched between the first electrode and the second electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 5, 2019
From: YAMADA, TAKAYOSHI; MIYAKE, YASUO; MURAKAMI, MASASHI
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 049673/0888 →
Priority Claims (1)
JP JP2018-013389 · Jan 30, 2018 · national
Continuity (1)
Related Publication 20190238768A1 · Aug 1, 2019
Cited By (1)
US 12,568,730